THEIVENDRAN, Premshanth et al.

Patent Trials and Appeals Board

Nov 29, 2019

14675403 - (D) (P.T.A.B. Nov. 29, 2019)

UNITED STATES PATENT AND TRADEMARK OFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
14/675,403 03/31/2015 Premshanth THEIVENDRAN MRVL-MP12721 5819
41066 7590 11/29/2019
MURABITO, HAO & BARNES LLP
111 NORTH MARKET STREET
Suite 700
SAN JOSE, CA 95113
EXAMINER
DOAN, NGHIA M
ART UNIT PAPER NUMBER
2851
MAIL DATE DELIVERY MODE
11/29/2019 PAPER
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte PREMSHANTH THEIVENDRAN, WEIHUANG WANG, GUY
HUTCHISON, and GERALD SCHMIDT
Appeal 2019-000615
Application 14/675,403
Technology Center 2800
BEFORE BEVERLY A. FRANKLIN, MICHAEL P. COLAIANNI, and
LILAN REN, Administrative Patent Judges.
REN, Administrative Patent Judge.
DECISION ON APPEAL1

1 The record on appeal includes the Specification of March 31, 2015 as well
as subsequent amendments (“Spec.”), the Examiner’s Final Action of
September 6, 2017 (“Final Act.”), Appeal Brief of March 5, 2018 (“Appeal
Br.”), and the Examiner’s Answer of July 25, 2018 (“Ans.”). No Reply
Brief was filed.
Appeal 2019-000615
Application 14/675,403
2
STATEMENT OF THE CASE
Pursuant to 35 U.S.C. § 134(a), Appellant2 appeals from the
Examiner’s decision to reject claims 1, 2, 4–6, 8–12, 14–16, 18–22, and 24–
30. Final Act. 2. We have jurisdiction under 35 U.S.C. § 6(b).
We AFFIRM.
CLAIMED SUBJECT MATTER
The Specification provides that the invention “generally relate[s] to
the field of electronic design automation tools for integrated circuit design”
and more specifically “electronic design automation tools for generating an
RTL description.” Spec.¶ 1. Claim 1, reproduced below, is illustrative of
the claimed subject matter:
1. A method, performed by a processor, for generating a
register transfer level (RTL) description using logical signal
grouping, the method comprising:
generating a plurality of logical interface definitions,
wherein the plurality of logical interface definitions define
signals from an output module to an input module and comprise
an interface rule;
defining a data structure in a structured document, wherein
the data structure comprises a first set of logical interfaces, and
wherein the structured document is used to define the logical
signal grouping for each logical interface of the first set of logical
interfaces;
executing an expansion script to generate a first RTL
description using the structured document, wherein the first RTL
description comprises a plurality of RTL modules that
communicate using the plurality of logical interface definitions,
and wherein the first RTL description is populated based on the

2 We use the word “Appellant” to refer to “Applicant” as defined in 37
C.F.R. § 1.42(a). Appellant identifies the real party in interest as CAVIUM,
INC. Appeal Br. 3.
Appeal 2019-000615
Application 14/675,403
3
plurality of logical interface definitions, the interface rule, and
the data structure;
modifying a first logical interface from the first set of
logical interfaces of the data structure to automatically generate
a second RTL description based on the expansion script using the
data structure defined in the structured document;
automatically generating an assertion based on the
structured document for testing a condition of a first RTL module
of the plurality of RTL modules, and
generating objects and sequence items based on the logical
signal grouping, wherein the generated objects and the generated
sequence items are to be used for error testing and use of drivers
and monitors.
REJECTIONS
Claims 1, 2, 4–6, 8–12, 14–16, 18–22, and 24–30 are rejected under
35 U.S.C. § 101. Final Act. 2.3
OPINION
Legal Framework
An invention is patent eligible if it claims a “new and useful process,
machine, manufacture, or composition of matter.” 35 U.S.C. § 101.
However, the Supreme Court has long interpreted 35 U.S.C. § 101 to include
implicit exceptions: “[l]aws of nature, natural phenomena, and abstract
ideas” are not patentable. E.g., Alice Corp. v. CLS Bank Int’l, 573 U.S. 208,
216 (2014).
In determining whether a claim falls within an excluded category, our
inquiry focuses on the Supreme Court’s two-step framework, described in
Mayo and Alice. Id. at 217–18 (citing Mayo Collaborative Servs. v.
Prometheus Labs., Inc., 566 U.S. 66, 75–77 (2012)). In accordance with

3 An obviousness rejection of claims 1, 2, 4–6, 8–12, 14–16, 18–22, and 24–
30 has been withdrawn. Ans. 2.
Appeal 2019-000615
Application 14/675,403
4
that framework, we first determine what concept the claim is “directed to.”
See Alice, 573 U.S. at 219 (“On their face, the claims before us are drawn to
the concept of intermediated settlement, i.e., the use of a third party to
mitigate settlement risk.”); see also Bilski v. Kappos, 561 U.S. 593, 611
(2010) (“Claims 1 and 4 in petitioners’ application explain the basic concept
of hedging, or protecting against risk.”).
Concepts determined to be abstract ideas, and thus patent ineligible,
include certain methods of organizing human activity, such as fundamental
economic practices (Alice, 573 U.S. at 219–20; Bilski, 561 U.S. at 611);
mathematical formulas (Parker v. Flook, 437 U.S. 584, 594–95 (1978)); and
mental processes (Gottschalk v. Benson, 409 U.S. 63, 69 (1972)). Concepts
determined to be patent eligible include physical and chemical processes,
such as “molding rubber products” (Diamond v. Diehr, 450 U.S. 175, 191
(1981)); “tanning, dyeing, making water-proof cloth, vulcanizing India
rubber, smelting ores” (id. at 182 n.7 (quoting Corning v. Burden, 56 U.S.
252, 267–68 (1853))); and manufacturing flour (Benson, 409 U.S. at 69
(citing Cochrane v. Deener, 94 U.S. 780, 785 (1876))).
In Diehr, the claim at issue recited a mathematical formula, but the
Supreme Court held that “[a] claim drawn to subject matter otherwise
statutory does not become nonstatutory simply because it uses a
mathematical formula.” Diehr, 450 U.S. at 176; see also id. at 191 (“We
view respondents’ claims as nothing more than a process for molding rubber
products and not as an attempt to patent a mathematical formula.”). Having
said that, the Supreme Court also indicated that a claim “seeking patent
protection for that formula in the abstract . . . is not accorded the protection
of our patent laws, . . . and this principle cannot be circumvented by
attempting to limit the use of the formula to a particular technological
Appeal 2019-000615
Application 14/675,403
5
environment.” Id. (citing Benson and Flook); see, e.g., id. at 187 (“It is now
commonplace that an application of a law of nature or mathematical formula
to a known structure or process may well be deserving of patent
protection.”).
If the claim is “directed to” an abstract idea, we turn to the second
step of the Alice and Mayo framework, where “we must examine the
elements of the claim to determine whether it contains an ‘inventive
concept’ sufficient to ‘transform’ the claimed abstract idea into a patent-
eligible application.” Alice, 573 U.S. at 221 (quotation marks omitted). “A
claim that recites an abstract idea must include ‘additional features’ to
ensure ‘that the [claim] is more than a drafting effort designed to
monopolize the [abstract idea].’” Id. (quoting Mayo, 566 U.S. at 77).
“[M]erely requir[ing] generic computer implementation[] fail[s] to transform
that abstract idea into a patent-eligible invention.” Id.
The Office recently published revised guidance on the application of
§ 101. USPTO’s January 7, 2019 Memorandum, 2019 Revised Patent
Subject Matter Eligibility Guidance (“Memorandum”), 84 Fed. Reg. 50.
Under that guidance, we first look to whether the claim recites:
(1) any judicial exceptions, including certain groupings of
abstract ideas (i.e., mathematical concepts, certain methods
of organizing human activity such as a fundamental
economic practice, or mental processes); and
(2) additional elements that integrate the judicial exception into a
practical application (see MPEP § 2106.05(a)–(c), (e)–(h)).
Only if a claim recites a judicial exception and does not integrate that
exception into a practical application, do we then look to whether the claim:
(3) adds a specific limitation beyond the judicial exception that
is not “well-understood, routine, conventional” in the field
(see MPEP § 2106.05(d)); or
Appeal 2019-000615
Application 14/675,403
6
(4) simply appends well-understood, routine, conventional activities
previously known to the industry, specified at a high level of
generality, to the judicial exception.
See generally Memorandum.
Analysis
Applying the guidance set forth in the Memorandum, we conclude
that claims 1, 2, 4–6, 8–12, 14–16, 18–22, and 24–30 do not recite patent-
eligible subject matter.
Revised Step 2A, Prong One–Directed to a Judicial Exception
The Memorandum instructs us first to determine whether each claim
recites any judicial exception to patent eligibility. 84 Fed. Reg. at 54. The
Memorandum identifies three judicially-excepted groupings: (1)
mathematical concepts, (2) certain methods of organizing human activity
such as fundamental economic practices, and (3) mental processes. Id. at 52.
We primarily focus here on the first grouping—mathematical concepts.
The Examiner finds that the claims are directed to a mental process or
mathematical algorithm. Final Act. 3; Ans. 12–13 (stating that the claims
are directed to “a mental process for generating circuit element descriptions
using conventional RTL and expansion scripts based descriptions of signal
interfaces between logic modules in a design”). Appellant, on the other
hand, argues that “the claimed invention specifies particular rules of defining
and grouping logic signals between the RTL modules in such a manner that
the physical components can be reused without implementing physical
changes to accommodate different placements, routings, and orientations in
RTL description generation.” Appeal Br. 15. (emphasis omitted). Appellant
reasons that “the claimed invention enables RTL modules to be
automatically populated using the expansion scripts and enables block
Appeal 2019-000615
Application 14/675,403
7
connectivity and functionality to be encapsulated and multiple interfaces to
be created instantly . . .[, and are] not directed to any abstract idea.” Id. at
16.
Claims 1, 2, 4–6, 8–12, 14–16, 18–22, and 24–30 recite that “the
generated sequence items are to be used for error testing and use of drivers
and monitors” and therefore are not directed to these structures. The claims
are rather directed to methods, “for generating a register transfer level (RTL)
description” which is, “[o]ne of the most common design abstractions in
digital circuit design.” Spec. ¶ 2. The RTL description, “models a digital
circuit based on the flow of digital signals (data) between hardware registers
and logical operations that are performed on those digital signals.” Id.
These methods are directed to, “a circuit design process” which is an
abstract idea of mental process or mathematical algorithm — as the
Examiner finds and Appellant does not address. See Ans. 12–13.
More specifically with regard to claim 1 which recites the following
steps: (1) “generating a plurality of logical interface definitions, wherein the
plurality of logical interface definitions define signals from an output
module to an input module and comprise an interface rule;” (2) “defining a
data structure in a structured document, wherein the data structure comprises
a first set of logical interfaces, and wherein the structured document is used
to define the logical signal grouping for each logical interface of the first set
of logical interfaces;” (3)
executing an expansion script to generate a first RTL
description using the structured document, wherein the first
RTL description comprises a plurality of RTL modules that
communicate using the plurality of logical interface definitions,
and wherein the first RTL description is populated based on the
plurality of logical interface definitions, the interface rule, and
the data structure;
Appeal 2019-000615
Application 14/675,403
8
(4) “modifying a first logical interface from the first set of logical interfaces
of the data structure to automatically generate a second RTL description
based on the expansion script using the data structure defined in the
structured document;” (5) “automatically generating an assertion based on
the structured document for testing a condition of a first RTL module of the
plurality of RTL modules;” and (6) “generating objects and sequence items
based on the logical signal grouping, wherein the generated objects and the
generated sequence items are to be used for error testing and use of drivers
and monitors.” These steps, under their broadest reasonable interpretation,
recite the steps to perform a, “design flow . . . for designing and fabricating
integrated circuits using logical signal grouping (LSG).” See Spec. ¶ 26.
Step (1) generates “a logical interface (i.e., input/output) description
to define a signal output and input using an interface rule” and is “written by
a register-transfer level (RTL) description which is one of the most common
design abstractions in digital circuit design.” Ans. 3 (citing Spec. ¶¶ 2, 3,
28, 29, and 36). Step (2) defines a data structure in a structured document
(e.g., XML, SGML, JSON, or CVS) that “contains information about the
signals, expressed in various data fields, including a ‘string’ field identifying
the names of individual signals, a ‘dir’ field identifying whether the signal is
an input or output, and an alias field describing the signal type/use[.]” Id. at
4 (citing Spec. ¶¶ 9, 28, 29, 34, and 36). The Specification provides an
exemplary logical signal grouping in Table II reproduced below as Figure 1:
Appeal 2019-000615
Application 14/675,403
9

Figure 1. An Image of Table II which provides an “exemplary logical signal
grouping (e.g., bus) for interface config_chain[.]” Spec. ¶ 35.

Step (3) uses “an expansion script (coding, software) to generate RTL
abstractions of circuit modules that include interfaces included in the
structured document and its associated data structure.” Ans. 5 (citing Spec.
¶¶ 9, 29, 31, 32, and 36). Figure 3A of the Specification, reproduced below,
provides such an expansion script:
Appeal 2019-000615
Application 14/675,403
10

Fig. 3A providing an “exemplary logical interface definitions and an
exemplary structured document used by expansion scripts to populate RTL
modules.” Spec. ¶ 14.

Step (4) modifies the abstract descriptions of logical interfaces from
step (1), and repeats the generation of RTL modules using an expansion
script. Ans. 6 (citing Spec. ¶¶ 31, 32, and 36). Step (5) provides additional
comments (i.e., assertion) in the first RTL to assign conditions. Id. (citing
Spec. ¶¶ 38, 39, and 41). “The assertions are represented as code that is
expanded using a macro based on the signals and structs of a structured
Appeal 2019-000615
Application 14/675,403
11
document.” Spec. ¶ 39. “During simulation, an interrupt/assertion is thrown
when a defined rule is violated. Assertions are used to detect errors early in
the design process to reduce debug time later in the process.” Id. ¶ 38.
Table III of the Specification “depicts automatically generated assertions
based on an exemplary structured document and interface definitions” and is
reproduced below as Figure 2:

Figure 2. An Image of Table III which “depicts automatically
generated assertions based on an exemplary structured document and
interface definitions.” Spec. ¶ 39.

Step (6) generates descriptions from existing information, that is,
“[f]rom the interface definitions previously described, various types of
objects can be generated based on the desired application. The data
structures used in SystemC, for example, closely mimic the interface
definitions in RTL.” Spec. ¶ 41; see also Ans. 7–8 (citing Spec. ¶¶ 38, 39,
and 41).
As the Specification provides, the claims describe a process of
“logical signal grouping [which] can be used to create objects for
verification purposes” that “enables easy bit-level manipulation in
SystemC.” Spec. ¶ 41. “Where RTL identifies interface transactions to
Appeal 2019-000615
Application 14/675,403
12
determine what data is being communicated between modules, software
designers views interfaces as objects that can be moved and assigned
values.” Id. ¶ 40. Appellant’s arguments that the recited process “specifies
particular rules of defining and grouping logic signals between the RTL
modules in such a manner that the physical components can be reused
without implementing physical changes to accommodate different
placements, routings, and orientations in RTL description generation”
(Appeal Br. 15 (emphasis removed)) which “enables automated reuse” of
RTL description modules (id. at 18 (emphasis removed)) do not contradict
the Examiner’s statement that generating “RTL descriptions from logical
interface descriptions and the structured document” is tantamount to the
mental process of “translating hardware descriptions.” Ans. 6–9. The
Specification similarly provides that in the prior art, “instances of RTL
modules are currently populated by hand without the automation provided
by encapsulating module connectivity and functionality using structured
code” which is contrasted with “the present invention [which] relate[s] to . . .
electronic design automation tools for . . . generating an RTL description.”
Spec. ¶¶ 1, 7.
The Specification also provides:
The interfaces of each module are generated based on the RTL
interface definitions and the logical signal grouping from the
structured document. For example, the RTL interface definition
of the first instance (instance 0) of the first dummy _ interface
includes “moda=datapath@”, where @ is associated with an
instance number, and modb=arbiter.

Spec. ¶ 31. Appellant does not address the Examiner’s reasoning that
establishing a mathematical relationship between dummy variables to
generate a RTL involves mathematical concepts. See Final Act. 3. We
Appeal 2019-000615
Application 14/675,403
13
agree with the Examiner that the claims recite a mental process and/or
mathematical concept, we find that the claims are directed to the judicial
exception of an abstract idea in the first prong of the revised Step 2A of the
2019 Guidelines. See Memorandum, 84 Fed. Reg. 51–52.
Revised Step 2A, Prong Two – Practical Application
Having determined that claims 1, 2, 4–6, 8–12, 14–16, 18–22, and 24–
30 are directed to the abstract idea of mental process and/or mathematical
concept, we next look to determine whether the claims recite “additional
elements that integrate the judicial exception into a practical application.”
MPEP § 2106.05(a)–(c), (e)–(h); Memorandum, 84 F.3d at 53–54.
Integration into a practical application requires an additional element or a
combination of additional elements in the claim to “apply, rely on, or use the
judicial exception in a manner that imposes a meaningful limit on the
judicial exception, such that the claim is more than a drafting effort designed
to monopolize the exception.” Memorandum, 84 Fed. Reg. at 53–54; see
also id. at 55 (setting forth exemplary considerations indicative that an
additional element or combination of elements may have integrated the
judicial exception into a practical application).
Here, the Examiner finds that the additional elements claims 1, 2, 4–6,
8–12, 14–16, 18–22, and 24–30 recite do not integrate the judicial exception
into a practical application. Final Act. 4; Ans. 16–18. The claims specify
that the steps are carried out by “a processor” — a generic computer. Ans.
9, 18 (“The claimed invention is directed to abstract ideas of generating RTL
description (i.e., using HDL generation and gate-level conversion) by using
conventional logic synthesis tools on a generic computer[.]”). Appellant
argues that “the claimed subject matter in independent claims does not
merely describe organizing and converting data to different data forms that
Appeal 2019-000615
Application 14/675,403
14
can be performed by a generic computer system” without explaining what
the recited “processor” may include other than a generic computer system.
Appeal Br. 21 (stating that the recited steps “tie the limitations of logic
signal grouping to the processor's ability to collect, compare, and organize”).
Appellant instead argues that the additional elements including, “defining
the logical signal grouping for a set of logical interfaces, and populating the
first RTL description based on the logical signal” which are the recited steps
carried out by the processor. Id. (emphasis removed). There are no
additional elements directed to a particular machine or transformation. The
claims do not require any step of using the result of the process — only the
intent for the generated RTL description, “to be used for error testing and
use of drivers and monitors.” The claims do not require any step of testing
or manufacturing a circuit. As the Examiner points out, the claims automate
a previously manual process by using a general purpose computer. Ans. 9,
13, and 17 (providing that “reusing and changing the RTL instance/module
can be done by human capabilities embodied as basic tools (i.e., a generic
computer, expansion scrip/code/program or conventional synthesis
tool/software in EDA), and are mental processes”); see also Spec. ¶ 39
(“The assertions are represented as code that is expanded using a macro
based on the signals and structs of a structured document. The assertions
may be automatically inserted into an RTL as in-line diagnostics code.”).
Appellant likewise acknowledges that the claims recite a computerized
process for automation, “without relying on a designer to manually find the
right solutions for accommodating different placements, routings, and
orientation.” Appeal Br. 21.
Appeal 2019-000615
Application 14/675,403
15
Step 2 B–Inventive Concept
Because we determine that claims 1, 2, 4–6, 8–12, 14–16, 18–22, and
24–30 are directed to an abstract idea and they do not include additional
elements that integrate the abstract idea into a practical application, we look
to whether each claim provides an inventive concept, i.e., adds a specific
limitation beyond the judicial exception that is not “well-understood,
routine, conventional” in the field. Memorandum, 84 Fed. Reg. at 56. There
is, however, none other than the abstract idea itself (i.e., carrying out the
mathematical concepts and performing mathematical operations) in the
claims. See Spec. ¶ 39 (“The assertions are represented as code that is
expanded using a macro based on the signals and structs of a structured
document. The assertions may be automatically inserted into an RTL as in-
line diagnostics code.”); see also Aatrix Software, Inc. v. Green Shades
Software, Inc., 890 F.3d 1354, 1359 (Fed. Cir. 2018) (holding that “the
‘inventive concept’ cannot be the abstract idea itself”).
Accordingly, we conclude that method claims 1, 2, 4–6, 8–12, 14–16,
18–22, and 24–30 are directed to patent ineligible subject matter under
35 U.S.C. § 101. Claims 1, 2, 4–6, 8–12, 14–16, 18–22, and 24–30 are
directed to the abstract idea of a mental process and/or mathematical concept
of, “design abstractions . . . which model[] a digital circuit based on the flow
of digital signals (data) between hardware registers and logical operations
that are performed on those digital signals” (Spec. ¶ 2) and do not recite
additional elements that integrate the mental process and/or mathematical
concept into a practical application. Further, the possible use of the method
in circuit design does not transform it into a patentable apparatus; the
method remains pre-empted mental process and/or mathematical concept.
Alice, 573 U.S. 208, 216 (“We have described the concern that drives this
Appeal 2019-000615
Application 14/675,403
16
exclusionary principle as one of pre-emption.”) (citing Bilski v. Kappos, 561
U.S. 593, 612 (2010) (“[U]pholding the patent ‘would pre-empt use of this
approach in all fields, and would effectively grant a monopoly over an
abstract idea.’”)).
CONCLUSION
The Examiner’s rejection is affirmed.
More specifically,
DECISION SUMMARY
Claims
Rejected
Basis Basis/References Affirmed Reversed
1, 2, 4–6,
8–12, 14–
16, 18–22,
and 24–30
§ 101 Eligibility 1, 2, 4–6,
8–12, 14–
16, 18–22,
and 24–30

Overall
Outcome
1, 2, 4–6,
8–12, 14–
16, 18–22,
and 24–30

FINALITY AND RESPONSE
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a). See 37 C.F.R.
§ 1.136(a)(1)(iv).

AFFIRMED