Monterey Research, LLC

Patent Trials and Appeals Board

Nov 30, 2021

IPR2020-00989 (P.T.A.B. Nov. 30, 2021)

Trials@uspto.gov Paper No. 42
571-272-7822 Date: November 30, 2021

UNITED STATES PATENT AND TRADEMARK OFFICE

BEFORE THE PATENT TRIAL AND APPEAL BOARD

ADVANCED MICRO DEVICES, INC.,
Petitioner,
v.
MONTEREY RESEARCH, LLC,
Patent Owner.

IPR2020-00989
Patent 6,765,407 B1

Before KRISTEN L. DROESCH, JOHN F. HORVATH, and
JASON W. MELVIN, Administrative Patent Judges.
MELVIN, Administrative Patent Judge.

JUDGMENT
Final Written Decision
Determining All Challenged Claims Unpatentable
35 U.S.C. § 318(a)
Dismissing Motion to Exclude
37 C.F.R. § 42.64(c)

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I. INTRODUCTION
Advanced Micro Devices, Inc., (“Petitioner”) filed a Petition (Paper 2,
“Pet.”) requesting institution of inter partes review of claims 1–3, 6–10,
13–17, and 20 (“the challenged claims”) of U.S. Patent No. 6,765,407 B1
(Ex. 1001, “the ’407 patent”). Monterey Research, LLC, (“Patent Owner”)
filed a Preliminary Response (“Prelim. Resp.”). Paper 9. After our email
authorization, Petitioner filed a Preliminary Reply (Paper 10) and Patent
Owner filed a Preliminary Sur-Reply (Paper 11). We instituted review.
Paper 13 (“Institution Decision” or “Inst.”).
Patent Owner filed a Response. Paper 20 (“PO Resp.”). Petitioner
filed a Reply. Paper 24 (“Pet. Reply”). Patent Owner filed a Sur-Reply.
Paper 29 (“PO Sur-Reply”). We held a hearing on September 1, 2021, and a
transcript appears in the record. Paper 41 (“Tr.”).
This is a final written decision as to the patentability of the challenged
claims. For the reasons discussed below, we determine Petitioner has shown
by a preponderance of the evidence that claims 1–3, 6–10, 13–17, and 20 of
the ’407 patent are unpatentable.
A. REAL PARTIES IN INTEREST
Petitioner identifies itself and ATI Technologies ULC as the real
parties in interest. Pet. 101. Patent Owner identifies itself and IPValue
Management as real parties in interest. Paper 5, 1.
B. RELATED MATTERS
The parties identify the following matters related to the ’407 patent:
Monterey Research, LLC v. Qualcomm Inc., No. 1:19-cv-02083-NIQA-LAS
(D. Del.); Monterey Research, LLC v. Advanced Micro Devices Inc., No.
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1:19-cv02149-NIQA-LAS (D. Del.); Monterey Research, LLC v. Marvell
Tech. Grp. Ltd., No. 1:20-cv-00158-NIQA-LAS (D. Del.); and Marvell
Semiconductor, Inc. v. Monterey Research, LLC, No. 3:20-cv-03296 (N.D.
Cal.). Pet. 101; Paper 5, 1.
C. THE ’407 PATENT
The ’407 patent describes a “digital configurable macro architecture.”
Ex. 1001, code (57). To that end, it describes “programmable digital circuit
blocks are 8-bit circuit modules that can be programmed to perform any one
of a variety of predetermined digital functions by changing the contents of a
few registers therein.” Id. at 2:4–7. As examples, the ’407 patent states that
its programmable blocks can be configured as “timers, counters, serial
communication ports, cyclic redundancy generators/checkers (CRC), or
pseudo random sequence generators (PRS).” Id. at 2:14–17. The blocks may
also be “coupled in series or in parallel to handle more complex digital
functions.” Id. at 2:21–23; accord id. at 6:29–43.
A particular block is configured in the ’407 patent “by changing the
contents of the configuration registers.” Id. at 2:35–37; accord id. at 4:55–
57. Thus, explains the patent, “configuration of the programmable digital
circuit block is fast and easy.” Id. at 2:34–35; accord id. at 4:59–63. In that
regard, the description contrasts the ’407 patent with field programmable
gate array (FPGA) devices, which it states “need to have their look-up tables
re-programmed in order to enable them to implement a new digital function,
which is a time consuming task.” Id. at 1:55–57; accord id. at 5:1–5.
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D. CHALLENGED CLAIMS
Challenged claim 1 is reproduced below:
1. A programmable digital device comprising:
a programmable digital circuit block that is configurable to
perform any one of a plurality of predetermined digital
functions upon being configured with a single register
write operation.
Ex. 1001, 8:35–39. Claims 8 and 15 are independent and recite limitations
similar to claim 1’s, claim 8 requiring an array of programmable digital
circuit blocks, and claim 15 expressing the elements as steps of a method. Id.
at 9:5–10, 10:5–15. The remaining challenged claims depend from one of
the independent claims. Id. at 8:35–10:37.
E. PRIOR ART AND ASSERTED GROUNDS
This proceeding involves the following grounds of unpatentability:
Claim(s) Challenged 35 U.S.C. §1 References/Basis
1, 7, 8, 14, 15 102 Mitra2
1–3, 6–10, 13–17, 20 103 Mitra
3, 8, 10, 13, 14, 17 103 Mitra, Munro3
2, 8, 9, 13, 14, 16 103 Mitra, Evans4
1–3, 6–10, 13–17, 20 103 Vorbach5

1 The Pre-AIA versions of 35 U.S.C. §§ 102 and 103 apply. See
MPEP § 2159.02.
2 US Pat. No. 5,577,235; iss. Nov. 19, 1996 (Ex. 1004).
3 US Pat. No. 5,506,484; iss. Apr. 9, 1996 (Ex. 1006).
4 US Pat. No. 4.049.953; iss. Sept. 20, 1977 (Ex. 1007).
5 US Pat. No. 6,728,871 B1; filed June 9, 1999; iss. Apr. 27, 2004
(Ex. 1005).
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Pet. 9. Petitioner relies also on the Declaration of David H. Albonesi, Ph.D.,
Ex. 1003.
II. ANALYSIS
A. LEVEL OF ORDINARY SKILL IN THE ART
Petitioner proposes that a person of ordinary skill “would have had a
bachelor’s degree in electrical or computer engineering, or a similar field
with at least two years of experience in digital circuit and computer design,
or a person with a master’s degree in electrical or computer engineering, or a
similar field with a specialization in digital circuit and computer design.”
Pet. 11 (citing Ex. 1003 ¶¶ 28–30). Patent Owner does not dispute this
definition of a person of ordinary skill. See generally PO Resp. We adopt
Petitioner’s proposed level of ordinary skill as it is consistent with the level
of skill reflected by the specification and in the asserted prior art references.
B. CLAIM CONSTRUCTION
For an inter partes review petition filed after November 13, 2018, we
construe claim terms “using the same claim construction standard that would
be used to construe the claim in a civil action under 35 U.S.C. 282(b).”
37 C.F.R. § 42.100(b) (2019).
Patent Owner submits that a “programmable digital circuit block”
means “digital circuit resources where a substantial amount of circuit
resources can be reused to perform a limited number of digital functions.”
PO Resp. 7–10. According to Patent Owner, that construction would
distinguish the claimed programmable digital circuit block from the circuit
blocks used in FPGAs. Id. at 7. Petitioner submits that no construction is
required, that Patent Owner attempts to import limitations from a preferred
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embodiment, and that the proposed construction would be indefinite for
lacking any objective boundaries. Pet. Reply 5–7.
Patent Owner’s arguments against Petitioner’s unpatentability
assertions help explain the proposed construction. Regarding Vorbach,
Patent Owner argues that because the asserted circuit block uses function
units performing unique functions (those functional units are not combined
but rather one is selected), Vorbach’s function units are not “reused” to
perform a set of predetermined functions. PO Resp. 71–72. Thus, Patent
Owner uses the term “reused” to mean that the claimed predetermined
digital functions must be performed using multiple resources within the
programmable digital circuit block. Patent Owner does not assert that its
proposed claim construction affects Petitioner’s assertions based on Mitra.
See id. at 14–69.
We determine it is not necessary to resolve whether Patent Owner’s
construction is correct because Petitioner shows that Vorbach discloses a
programmable digital circuit block such that a substantial amount of digital
circuit resources can be reused to perform a limited number of digital
functions. See infra at 11; Nidec Motor Corp. v. Zhongshan Broad Ocean
Motor Co., 868 F.3d 1013, 1017 (Fed. Cir. 2017) (holding that claims need
be construed only to the extent a construction is material to a dispute).
C. OBVIOUSNESS OVER VORBACH
Vorbach discloses a “cascadable arithmetic and logic unit (ALU)
which is configurable in function and interconnection.” Ex. 1005, code (57).
Vorbach’s system comprises cells, termed processing array elements (PAE),
combined into an array, and a primary logic unit (PLU) that configures the
array. Id. at 3:33–38, 6:65–7:3. Vorbach’s Figure 1 is reproduced below:
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Id., Fig. 1. Figure 1 depicts an array of PAEs 103, each connected to
PLU 101 through the PLU bus system 102, and also connected to the other
PAEs through internal bus system 104. Id. at 9:33–37.
Vorbach explains that, although the PAEs are cells based on
conventional FPGA cells, “[a]n expanded arithmetic and logic unit (EALU)
with special extra functions is integrated into this cell to perform the data
processing.” Id. at 2:31–36, 3:33–38. The “EALU is capable of performing a
plurality of arithmetic and logic operations.” Id. at 3:44–45.
Vorbach contrasts its approach with conventional FPGA devices,
which Vorbach explains “usually include multiplexers or look-up table
(LUT) architectures” that require extensive configuration. Id. at 1:49–55
(“Large volumes of data are required, necessitating a comparably large
amount of time for configuration and reconfiguration.”). In contrast,
Vorbach’s ALU “can be reconfigured at run time without any effect on
surrounding ALU’s, processing units or data streams.” Id. at 2:19–21. Thus,
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Vorbach’s design seeks to achieve short configuration times by
supplementing a conventional FPGA cell with an EALU configured by a
function register. Id. at 2:30–38. Vorbach explains that “[t]he EALU is
configured by a function register which greatly reduces the volume of data
required for configuration.” Id. at 2:36–38; accord id. at 3:63–64 (“The
function of the EALU is configured in a function register (F-PLUREG).”).
To configure the interconnection of a PAE with other PAEs in the array,
Vorbach provides a separate register, M-PLUREG. Id. at 9:3–4.
Vorbach’s Figure 2 is reproduced below:

Id. Fig. 2. Figure 2 depicts the schematic architecture of a PAE, including
PLU bus 210 connected to F-PLUREG 0211 controlling EALU 0208 and
connected to M-PLUREG 0203 controlling BM-UNIT 0202, which connects
to system bus 0201. Id. at 9:39–59. Figure 2 further shows the PAE includes
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registers and multiplexers for managing data provided from internal bus 201
and resulting from the EALU’s operation. Id. at 9:39–49.
1. Claim 1
Petitioner maps claim 1’s programmable digital circuit block to
Vorbach’s EALU and, alternatively, to its PAE. Pet. 60. Petitioner asserts
that the EALU/PAE is configured by a single write operation to the F-
PLUREG. Id. at 63–65 (citing, e.g., Ex. 1005, 3:63–64 (“The function of the
EALU is configured in a function register (F-PLUREG).”), 9:52–53 (“F-
PLUREG contains all functional configuration data . . . .”). Petitioner points
out that, within the F-PLUREG, five bits configure the EALU function.
Pet. 63 (citing Ex. 1005, 8:1–35).
Vorbach describes that the F-PLUREG is “connected to the PLU bus”
and that the PLU may address a particular PAE and select its F-PLUREG or
M-PLUREG for access. Ex. 1005, 7:45–50. Petitioner relies on Vorbach’s
statement that, when the PLU sends data to a PAE with the F-PLUREG
selected, “[t]he data are stored in the respective register at the rising edge of
DEN,” which occurs once during a write operation. Pet. 65 (quoting
Ex. 1005, 9:60–10:7 (referring to “data enable” signal); citing 7:45–48,
7:61–65, 17:7–9, Figure 3; Ex. 1003 ¶¶ 179–180). Petitioner also argues that
“the F-PLUREG register (12 bits) is smaller than the PLU bus width
(24 bits) and thus is obviously written with a single register write operation.”
Id. (citing Ex. 1005, 7:44–8:35; Ex. 1003 ¶ 181).
Petitioner recognizes that Vorbach further discloses embodiments
containing multiple F-PLUREGs within a single PAE. Pet. 66–67. Petitioner
points out that such embodiments with multiple F-PLUREGs are optional
and do not impact the embodiment relied on here. Id. at 67–68. Petitioner
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further contends that, even in such embodiments, only a single F-PLUREG
is used at a time. Id. at 69 (citing Ex. 1005, 14:3–15:4, 15:47–53, 16:7–26,
Fig. 2). Similarly, Petitioner recognizes that Vorbach discloses “features for
interconnecting multiple PAEs through an ‘internal bus’ (0104).” Id. at 70.
That interconnection is configured using the M-PLUREG, which Figure 2
shows is connected only to the bus multiplexer unit (BM-Unit), which
controls data flow in and out of the PAE. Id. at 70–72 (citing Ex. 1005,
6:20–29, 12:31–35, 16:49–55, 8:53–67, Figs. 2, 12). Therefore, according to
Petitioner, Vorbach’s interconnection features, including configuration of
M-PLUREG, do not impact how a PAE’s independent operation renders the
claim language obvious. Id. at 70–72.
We determine that Vorbach’s disclosures regarding its PAE are
persuasive. Certain of Patent Owner’s arguments address whether Vorbach’s
EALU alone satisfies the claim language. See PO Sur-Reply 21–23. We
address Petitioner’s contentions regarding a PAE containing an EALU, and
therefore do not address Patent Owner’s arguments limited to the EALU
alone.
Patent Owner argues that Vorbach’s “PAE/EALU” is not a
programmable digital circuit block because it does not reuse a sufficient
number of circuit resources when implementing the different possible
functions. PO Resp. 70–72. In that regard, Patent Owner relies on its
proposed claim construction, which we discuss above. See supra at 5.
Because the EALU contains “function units” where only one such unit is
selected at a time, Patent Owner submits that the EALU cannot be a
programmable digital circuit block. PO Resp. 71–72 (citing Ex. 1003 ¶ 183;
Ex. 2003, 131:9–25, 132:8–14, 136:5–17). Patent Owner applies that same
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conclusion to Vorbach’s PAE, apparently because the EALU function units
perform operations within the PAE. See id. (treating the PAE the same as the
EALU).
As noted, Vorbach’s PAE includes multiple registers and multiplexers
used to perform the various functions in conjunction with the EALU. See
Pet. Reply 27 (citing Ex. 1008, 128:25–129:8, 131:10–14, 127:25–128:24,
129:18–130:11, 130:21–131:9; Ex. 1005, 3:40–4:35, 9:39–47, 14:6–52,
15:5–21, 17:52–18:31, Figs. 2, 17–18). Patent Owner’s proposed
construction does not limit which resources must be reused across different
functions, nor does Patent Owner provide guidance regarding how such a
determination would be made. See PO Resp. 7–9. By reusing the registers
and multiplexers across the various EALU functions that a PAE may
perform, the PAE reuses a substantial amount of its circuit resources and
therefore satisfies Patent Owner’s proposed construction.
We recognize that Patent Owner attempts to craft its construction such
that it would exclude FPGA devices. See PO Resp. 7–8. Although Vorbach
states that it is directed to the architecture of a cell such as a “conventional
FPGA cell[],” it further describes that the cell integrates an EALU “with
special extra functions . . . to perform the data processing.” Ex. 1005, 2:31–
36. Thus, Vorbach does not describe a conventional FPGA device, but rather
an improvement over such devices. In contrast to FPGA devices, Vorbach’s
“EALU is configured by a function register which greatly reduces the
volume of data required for configuration.” Id. at 2:36–38.
Patent Owner argues that various disclosures in Vorbach show that
more than a single register write operation is required for configuration. In
particular, Patent Owner points to three aspects: (1) a “config state machine”
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that participates in configuration; (2) configuration required for the PLU
(which configures a PAE); and (3) a write to the M-PLUREG register.
PO Resp. 73–83.
Vorbach discloses a “config state machine” that “manages the
configuration registers” (see Ex. 1005, 15:32–46), which Patent Owner
characterizes as performing multiple configuration write operations such that
Vorbach does not teach configuring the PAE with a single register write
operation (see PO Resp. 74–79). We are persuaded, however, by Petitioner’s
argument that the config state machine relates to the optional embodiment
depicted in Figure 17, which includes three F-PLUREGs and uses an
additional PAE (the “config PAE”) in conjunction with the “config state
machine” to select from multiple possible F-PLUREGs. Stated simply, in a
circuit having a single F-PLUREG, as in Vorbach’s Figure 2, no config state
machine is required. Pet. Reply 36–39.
Patent Owner argues additionally that, even with a single F-PLUREG,
the config state machine “transmits a stop signal to the sync unit of the
PAE” to prepare the PAE for reconfiguration. PO Resp. 76–77. We do not
agree for two reasons: (1) that discussion arises in Vorbach’s discussion of
selecting from multiple F-PLUREGs (Ex. 1005, 15:32–46), and (2) Patent
Owner has shown, at most, that Vorbach’s sync unit relates to changing the
PAE operational state, not its configuration (see Tr. 19:24–21:15). Further,
Patent Owner’s arguments regarding Vorbach’s config state machine relate
to reconfiguring a PAE following some degree of operation, not an initial
configuration. See PO Resp. 74 (arguing the sync unit “monitors the
reconfiguration of PAEs” (quoting Ex. 1005, 18:43–47)), 76 (arguing the
stop signal regulates “the readiness for reconfiguration” (quoting Ex. 1005,
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13:7–10)); see also Pet. Reply 29–30. We therefore conclude that Vorbach’s
discussion of a config state machine does not undermine Petitioner’s
showing that Vorbach’s PAE is configured with a single register write
operation.
Patent Owner raises an argument based on Vorbach’s discussion of a
OneShot mode. PO Resp. 78. Vorbach, however, states that OneShot is “a
special mode which enables the clock signal only when operands are
available.” Ex. 1005, 5:61–62. We do not agree with Patent Owner that
Vorbach’s optional features, such as OneShot mode, impact Petitioner’s
showing. Indeed, while OneShot mode is controlled by two bits in
F-PLUREG, the default state of 00 for those bits results in “Normal
function,” indicating that OneShot need not be invoked for F-PLUREG to
configure the PAE as claimed. See Ex. 1005, 8:23–26.6
Patent Owner argues that because Vorbach’s PAE is itself configured
by the PLU, and the PLU is “[c]onfigured by a microcontroller adapted
specifically to its task,” the PAE is not configured by a single register write
operation. PO Resp. 79. The PLU, however, is not part of the claimed
“programmable digital circuit block” and therefore does not impact whether
the PAE is configured with a single register write operation. See
Pet. Reply 39.

6 As Petitioner points out (Pet. Reply 30), the same is true for the
F-PLUREG Stop bit, which need not be written before the EALU function
bits. Ex. 1005, 8:15–16 (showing the “0” state of the Stop bit corresponds
to “Normal function); see PO Resp. 77 (“If STOP is set before the EALU
function bits, then configuration requires at least two register write
operations of the F-PLUREG. If set at the same time, this shows that the
Config-SM is required for writing to F-PLUREG.” (emphasis omitted)).

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Finally, Patent Owner argues that Vorbach’s M-PLUREG is another
register required for configuration. PO Resp. 80–83. We do not agree. The
M-PLUREG register configures interconnections for a PAE to interact with
other similar elements. Ex. 1005, 9:3–4, 9:52–54 (“F-PLUREG contains all
functional configuration data, M-PLUREG contains the interconnection
information of the PAE.”). The claim language is directed to a circuit block
“configurable to perform any one of a plurality of predetermined digital
functions.” Petitioner identifies a predetermined number of functions in a
PAE (using the EALU) that may be configured using only F-PLUREG
(Pet. 61), and any further configuration using M-PLUREG to enable a PAE
to interact with other array elements does not bear on the claim language.
We agree with Petitioner that much of what Patent Owner identifies to
support its position relates to communications using Vorbach’s internal bus,
which does not write to F-PLUREG. See Pet. Reply 30–35. Vorbach
discloses the PLU communicates using PLU bus 210, including writes to the
F-PLUREG and M-PLUREG registers, such that the PAE is configured over
the PLU bus 210. Ex. 1005, 9:48–52. The PAE also communicates using
internal bus system 201, which allows data to move in and out of the PAE;
results from the EALU are also sent to the PLU over the PLU bus using
state-back UNIT 209. Id. at 9:39–48. Notwithstanding the internal bus
communications, Vorbach discloses that “F-PLUREG contains all functional
configuration data” and that only PLU bus 210 permits communication with
F-PLUREG. Id. at 9:52–53, Fig. 2. Thus, Vorbach supports that the PAE’s
functional configuration is determined by the F-PLUREG register and that
F-PLUREG is controlled over the PLU bus.
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In sum, for the reasons discussed above, we agree with Petitioner that
Vorbach teaches configuring the PAE using a single register write operation,
namely, a single write to F-PLUREG.
2. Claims 7 and 14
Claims 7 and 14 depend from independent claims 1 and 8,
respectively, and further recite:
a configuration register for receiving and storing a plurality
of configuration data corresponding to any of said
plurality of predetermined digital functions, and
a plurality of selectable logic circuits which perform any of
said plurality of predetermined digital functions,
wherein said predetermined digital functions determine
size and arrangement of said selectable logic circuits.
Ex. 1001, 8:62–9:4, 9:33–10:4. Petitioner asserts that Vorbach’s F-PLUREG
renders obvious the claimed configuration register (Pet. 84–87), and that
“function units” implementing the EALU’s digital functions render obvious
the claimed plurality of selectable logic circuits (id. at 87–92).
Patent Owner challenges Petitioner’s showing as to the plurality of
selectable logic circuits, arguing that, because “Vorbach does not teach how
its function units actually implement the functions,” skilled artisans would
not know “whether different functions result in different sizes and
arrangement of the underlying circuits within a function unit.” PO Resp. 84.
Patent Owner suggests that because implementations may vary, the circuit
designer, not the predetermined digital functions, would control size and
arrangement of the logic circuits. Id. at 84–85.
Petitioner points out that Vorbach describes that its “EALU is an
ordinary known arithmetic and logic unit (ALU) which has been expanded
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by special functions such as counters” and that the “plurality of arithmetic
and logic operations . . . do not have to be specified here exactly, because it
is possible to refer to known ALUs.” Ex. 1005, 3:40–47; see Pet. Reply 40.
We agree that Vorbach’s EALU includes reusable components that were
well known to skilled artisans at the time.
Vorbach discloses that the EALU “function units include a divider
(1807), a multiplier (1817), an adder/comparator (1809), logic functions
(1810), a shift register (1811) and a counter (1812).” Ex. 1005, 15:11–14.
And Patent Owner’s declarant agreed, for example, that given the same
“technology used to implement the circuit[s],” “[t]he size of a multiplier
circuit would obviously be different than the size of an adder/comparator
circuit.” Ex. 1008, 136:19–25; accord id. at 137:10–138:5 (agreeing with the
same conclusion regarding the various circuits used in Vorbach’s EALU).
He further agreed that the different circuits disclosed in Vorbach’s EALU
would use different arrangements of components. Id. at 138:6–139:21.
Based on the foregoing, we find that Vorbach discloses that the
predetermined digital functions performed by its EALU function units
determine the size and arrangement of said selectable logic circuits (e.g.,
adder, multiplier, shift register) that perform those predetermined digital
functions.
3. Objective Indicia of Nonobviousness
Patent Owner submits that the ’407 patent’s claimed invention
“solved a long-felt need, specifically the need for a configurable computer
architecture without the programming overhead and inefficiency of an
FPGA.” PO Resp. 86. Patent Owner asserts benefits of the ’407 patent’s
approach, citing exclusively to the specification. Id. at 86–88. It then
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concludes that “[t]hese benefits, which were not provided in the prior art,
support the nonobviousness of the claimed invention.” Id. at 89 (citing
Ex. 2002 ¶ 188). The support cited is Patent Owner’s declarant, making the
same statement included in the Response. See Ex. 2002 ¶ 188.
Petitioner asserts that, because Vorbach provided the same solution
and benefits that the ’407 patent purports to provide, there was no unmet
need by the time of the ’407 patent. Pet. Reply 41. As discussed above, we
agree with Petitioner that Vorbach discloses configuration of a
programmable digital circuit block using a single register write operation.
See supra at 11–15. Vorbach therefore solved the need that Patent Owner
asserts, prior to invention of the ’407 patent.7
4. Conclusion
As discussed, and based on Petitioner’s contentions (see Pet. 56–73),
we find that Vorbach teaches all limitations of claim 1. We have considered
Patent Owner’s assertions regarding objective indicia of nonobviousness,
together with Petitioner’s submissions regarding Vorbach, and conclude that
the subject matter of claim 1 would have been obvious over Vorbach.
As discussed, we find that Vorbach teaches the additional limitations
of claims 7 and 14. We have considered Patent Owner’s assertions regarding

7 Even if we had not concluded that Patent Owner’s asserted need was
already met before the challenged patent, Patent Owner has not identified
objective evidence to support its view. Citations to the challenged patent’s
specification do not offer a reliable basis on which to conclude that the
claims were nonobvious, and Patent Owner’s declarant provides no
additional evidence to support his statements. See Ex. 2002 ¶¶ 183–188; 37
C.F.R. § 42.65(a) (“Expert testimony that does not disclose the underlying
facts or data on which the opinion is based is entitled to little or no
weight.”); Pet. Reply 41.
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objective indicia of nonobviousness, together with Petitioner’s submissions
regarding Vorbach, and conclude that the subject matter of claims 7 and 14
would have been obvious over Vorbach.
For claims 2, 3, 6, 8–10, 13, 15–17, and 20, Petitioner provides
contentions showing how Vorbach teaches each of the elements recited in
these claims. Pet. 73–100. Other than as addressed above regarding claims 1,
7, and 14, Patent Owner does not challenge Petitioner’s contentions
regarding Vorbach’s disclosures with respect to claims 2, 3, 6, 8–10, 13, 15–
17, or 20. See PO Resp. 69–85. We determine Patent Owner has waived any
such argument regarding these claims. See Paper 14, 8 (“Patent Owner is
cautioned that any arguments not raised in the response may be deemed
waived.”); In re NuVasive, Inc., 842 F.3d 1376, 1380–81 (Fed. Cir. 2016);
Consolidated Trial Practice Guide 52 (Nov. 2019). We have reviewed the
parties’ contentions and the evidence presented, including objective
evidence of nonobviousness, and conclude that Petitioner has shown by a
preponderance of the evidence that the subject matter of each of claims 2, 3,
6, 8–10, 13, 15–17, and 20 would have been obvious over Vorbach.
D. GROUNDS INCLUDING MITRA
Petitioner also challenges claims 1–3, 6–10, 13–17, and 20 as
anticipated or rendered obvious over Mitra alone or in combination with
Munro or Evans. See Pet. 12–56. We need not determine the merits of those
challenges because, as explained above, Petitioner has demonstrated the
unpatentability of those claims over Vorbach. See Beloit Corp. v. Valmet Oy,
742 F.2d 1421, 1423 (Fed. Cir. 1984) (finding an administrative agency is at
liberty to reach a decision based on a single dispositive issue because doing
so “can not only save the parties, the [agency], and [the reviewing] court
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Patent 6,765,407 B1

19
unnecessary cost and effort,” but can “greatly ease the burden on [an
agency] faced with a . . . proceeding involving numerous complex issues and
required by statute to reach its conclusion within rigid time limits”).
E. PETITIONER’S MOTION TO EXCLUDE EX. 2008
Petitioner moves to exclude Exhibit 2008, which Patent Owner filed
with the Patent Owner Sur-Reply. Paper 31. We do not rely on Exhibit 2008
in any regard in this Decision, and therefore dismiss Petitioner’s motion as
moot.
III. CONCLUSION8
For the reasons discussed, we conclude:
Claim(s)

35
U.S.C.
§
Reference(s)/Basis
Claim(s)
Shown
Unpatentable
Claim(s)
Not Shown
Unpatentable
1, 7, 8,
14, 15 102 Mitra Not decided Not decided
1–3, 6–
10, 13–
17, 20
103 Mitra Not decided Not decided
3, 8, 10,
13, 14, 17 103 Mitra, Munro Not decided Not decided
2, 8, 9,
13, 14, 16 103 Mitra, Evans Not decided Not decided

8 Should Patent Owner wish to pursue amendment of the challenged claims
in a reissue or reexamination proceeding subsequent to the issuance of this
decision, we draw Patent Owner’s attention to the April 2019 Notice
Regarding Options for Amendments by Patent Owner Through Reissue or
Reexamination During a Pending AIA Trial Proceeding. See 84 Fed. Reg.
16,654 (Apr. 22, 2019). If Patent Owner chooses to file a reissue
application or a request for reexamination of the challenged patent, we
remind Patent Owner of its continuing obligation to notify the Board of
any such related matters in updated mandatory notices. See 37 C.F.R.
§ 42.8(a)(3), (b)(2).
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Patent 6,765,407 B1

20
Claim(s)

35
U.S.C.
§
Reference(s)/Basis
Claim(s)
Shown
Unpatentable
Claim(s)
Not Shown
Unpatentable
1–3, 6–
10, 13–
17, 20
103 Vorbach 1–3, 6–10, 13–17, 20
Overall
Outcome
1–3, 6–10,
13–17, 20
IV. ORDER
It is
ORDERED that Petitioner has proven that claims 1–3, 6–10, 13–17,
and 20 of the ’407 patent are unpatentable;
FURTHER ORDERED that Petitioner’s Motion to Exclude
Exhibit 2008 is dismissed as moot; and
FURTHER ORDERED that, because this is a Final Written Decision,
parties to the proceeding seeking judicial review of the decision must
comply with the notice and service requirements of 37 C.F.R. § 90.2.

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Patent 6,765,407 B1

21

PETITIONER:

Harper Batts
Jeffrey Liang
Chris Ponder
SHEPPARD, MULLIN, RICHTER & HAMPTON LLP
hbatts@sheppardmullin.com
jliang@sheppardmullin.com
cponder@sheppardmullin.com

PATENT OWNER:

Theodoros Konstantakopoulos
Kevin McNish
DESMARAIS LLP
tkonstantakopoulos@desmaraisllp.com
kkm-ptab@desmarisllp.com