Ex Parte Yeh et al

Patent Trial and Appeal Board

Dec 11, 2012

11285614 (P.T.A.B. Dec. 11, 2012)

UNITED STATES PATENT AND TRADEMARK OFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
11/285,614 11/21/2005 Chih Chieh Yeh MXIC 1553-9 9468
46353 7590 12/12/2012
MACRONIX
C/O HAYNES BEFFEL & WOLFELD LLP
P. O. BOX 366
HALF MOON BAY, CA 94019
EXAMINER
DUONG, KHANH B
ART UNIT PAPER NUMBER
2822
MAIL DATE DELIVERY MODE
12/12/2012 PAPER
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
PTOL-90A (Rev. 04/07)

UNITED STATES PATENT AND TRADEMARK OFFICE
________________

BEFORE THE PATENT TRIAL AND APPEAL BOARD
________________

Ex parte CHIH CHIEH YEH, HAN CHAO LAI,
WEN JER TSAI, TAO CHENG LU, and CHIH YUAN LU

________________

Appeal 2010-007920
Application 11/285,614
Technology Center 2800
________________

Before ERIC B. CHEN, TREVOR M. JEFFERSON, and JOHN G. NEW,
Administrative Patent Judges.

NEW, Administrative Patent Judge.

DECISION ON APPEAL

Appeal 2010-007920
Application 11/285,614

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SUMMARY
Appellants file this appeal under 35 U.S.C. § 134(a) from the
Examiner’s Final Rejection of claims 1-15 as unpatentable under 35 U.S.C.
§ 103(a). Specifically, claims 1-5, 9, and 11-15 stand rejected under 35
U.S.C. § 103(a) as being obvious over Knall et al. (US 6,704,235 B2,
March 9, 2004) (“Knall”) and Vyvoda et al. (US 6,490,218 B1, December
3, 2002) (“Vyvoda”). Claim 6 stands rejected under 35 U.S.C. § 103(a) as
being obvious over Knall, Vyvoda, and Van Brocklin et al. (US 6,534,841
B1, March 18, 2003) (“Van Brocklin”). The Examiner additionally rejected
claims 7, 8, and 10 under 35 U.S.C. § 103(a) as being obvious over Knall,
Vyvoda, and Madurawe (US 6,713,839 B2, March 30, 2004)
(“Madurawe”).
We have jurisdiction under 35 U.S.C. § 6(b).
We affirm.

STATEMENT OF THE CASE
Appellants’ invention is directed to a method for manufacturing an
electrically programmable non-volatile memory cell comprising forming a
first electrode on a substrate, forming an inter-electrode layer of material on
the first electrode having a property which is characterized by progressive
change in response to stress, and forming a second electrode over the inter-
electrode layer of material. The inter-electrode layer comprises a dielectric
layer. Abstract.

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GROUPING OF CLAIMS

Claims 2-14 depend from claim 1. Because Appellants argue that the
Examiner erred for substantially the same reasons with respect to
independent claims 1 and 15, as well as dependent claims 2-20, we select
claim 1 as representative of the claims on appeal. Claim 1 recites:
1. A method for manufacturing a memory cell, where data is
stored by setting a property of the memory cell above or below a
set of two or more reference levels to store a multiple bit data
value, comprising:

forming a first electrode;

forming an inter-electrode layer of material on the first
electrode, the inter-electrode layer of material having an property
characterized by progressive change in response to stress; and

forming a second electrode over the inter-electrode layer of
material on the first electrode, wherein said stress comprises
voltage less than 5 volts across the first and second electrodes;
and

providing circuitry coupled to the memory cell to set said
property above or below reference levels in said set of reference
levels to store a multiple bit data value in the memory cell in
response to multiple bit input data.

App. Br.13.

ISSUE

Appellants argue that the Examiner erred in finding that claim 1 is
unpatentable under 35 U.S.C. § 103(a) as being obvious over Knall and
Vyvoda. App. Br. 9. Specifically, Appellants argue that the Examiner
erred because the Examiner finds that the combination of Knall and Vyvoda
discloses or suggests the limitation of claim 1 reciting “the inter-electrode
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Application 11/285,614

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layer of material having an [sic] property characterized by progressive
change in response to stress.” App. Br. 9. We therefore address the issue
of whether the Examiner erred in finding that the combination of Knall and
Vyvoda discloses or suggests that limitation.

ANALYSIS
Appellants argue that the plain meaning of “progressive change,” as
described in the Specification, is a “gradual, nearly linear change.” Reply
Br. 5 (citing Specification, ¶¶ [0076], [0077]). According to Appellants, Knall
teaches the rupture or breakage of a central antifuse layer located between two
electrodes, and is explicit in teaching that the antifuse layer is either ruptured
or is not. App. Br. 10; Reply Br. 5. Appellants contend that it is nonsensical
to use such an anti-fuse capable of storing a single bit value (either a ruptured
high conductivity state or a not-ruptured low conductivity state) to store a
multiple-bit value (the number of pulses required to rupture the anti-fuse).
App. Br. 11.
Appellants further argue that Vyvoda also fails to teach circuitry that
sets a property characterized by a progressive change. Reply Br. 6. According
to Appellants, Vyvoda discloses three disparate threshold current values,
resulting in much wider margins between data values as further breakdown of
the inter-electrode layer’s resistance occurs, and that the Vyvoda memory cells
therefore rely on “hard,” rather than “progressive” breakdown in memory
cells. Reply Br. 6-7.
The Examiner responds that Knall discloses the same antifuse material
(i.e., silicon dioxide) for its inter-electrode layer of material as does the
claimed invention. Ans. 7 (citing Knall, col. 4, ll. 4-9, col. 10, ll. 34-39). The
Examiner also finds that Vyvoda teaches providing circuitry comprising two
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electrodes coupled by an antifuse (e.g. silicon oxide) memory cell (MCI ...
MCN) “to set a property (electrical resistance) of the memory cell above or
below a set of two or more reference levels (Tl to T3) to store a multiple bit
data value (2 or more bits) in the memory cell in response to multiple bit input
data (WSI ... WS3).” Ans. 7 (quoting Vyvoda, Figs. 4-6, cols. 2-4, ll. 35-54).
Consequently, according to the Examiner, it would have been obvious to a
person of ordinary skill in the contemporaneous art to modify the method of
Knall with the teaching of Vyvoda because of the desirability to maximize
data storage density of the anti-fuse memory array. Ans. 8.
We are not persuaded by Appellants’ argument that the Examiner erred
in finding that the limitation of claim 1 reciting “the inter-electrode layer of
material having an [sic] property characterized by progressive change in
response to stress” is disclosed or suggested by the combination of Knall
and Vyvoda. We agree with Appellants that Knall teaches an inter-
electrode layer of antifuse that is either ruptured or is not. Reply Br. 5
(citing Knall, col. 1, ll. 26-37) (“The anti-fuse layer is initially intact, but it
can be ruptured or broken by applying a sufficient voltage across the
memory cell”). However, Vyvoda also teaches an inter-electrode layer, one
that is characterized by progressive change in response to stress. Figure 4
of Vyvoda discloses an inter-electrode layer (MC1-MCN). Ans. 7. Figure
7 of Vyvoda discloses a graph of an exemplary relationship between the
write current Iw used to program a selected memory cell and the associated
read current IR that is measured when a 2 volt read voltage RV is applied to
the selected memory cell: the relationship depicted between IR and Iw is that
of a gradual, nearly linear change. Ans. 7; see also Vyvoda, col. 3, ll. 46-
50. Moreover, Vyvoda explicitly teaches that “[t]he state of a memory cell
is read by applying a voltage across the memory cell and then making a
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measurement of a parameter that varies in accordance with the resistance
of the memory cell, such as a measurement of voltage, current or power.”
Vyvoda, col. 4, ll. 10-14) (emphasis added).
We find that these teachings of Vyvoda, as cited by the Examiner, in
combination with the teachings of Knall, disclose or suggest the limitation
of claim 1 reciting “the inter-electrode layer of material having an [sic]
property characterized by progressive change in response to stress.” We
therefore conclude that the Examiner did not err in concluding that the
recited limitation is unpatentable under 35 U.S.C. § 103(a) as being obvious
over the combination of Knall and Vyvoda.

DECISION
The Examiner’s decision to reject claims 1-20 is affirmed.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(1). See 37 C.F.R.
§ 1.136(a)(1)(iv) (2011).

AFFIRMED

ELD