Ex Parte Ramachandran et al

Patent Trial and Appeal Board

May 21, 2018

14499151 (P.T.A.B. May. 21, 2018)

UNITED STA TES p A TENT AND TRADEMARK OFFICE
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR
14/499,151 09/27/2014 Vidhya RAMACHANDRAN
12371 7590 05/23/2018
Muncy, Geissler, Olds & Lowe, P.C./QUALCOMM
4000 Legato Road, Suite 310
Fairfax, VA 22033
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www .uspto.gov
ATTORNEY DOCKET NO. CONFIRMATION NO.
QC141584 4100
EXAMINER
MOORE, WHITNEY
ART UNIT PAPER NUMBER
2826
NOTIFICATION DATE DELIVERY MODE
05/23/2018 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address( es):
meo.docket@mg-ip.com
meo@mg-ip.com
ocpat_uspto@qualcomm.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte VIDHY A RAMA CHAND RAN and URMI RAY
Appeal2017-007358
Application 14/499,151
Technology Center 2800
Before BRADLEY R. GARRIS, JAMES C. HOUSEL, and
DONNA M. PRAISS, Administrative Patent Judges.
PRAISS, Administrative Patent Judge.
DECISION ON APPEAL 1
STATEMENT OF THE CASE
This is an appeal under 35 U.S.C. § 134(a) from the final rejection of
claims 1, 4--12, and 15-25. We have jurisdiction under 35 U.S.C. § 6.
We AFFIRM.
The subject matter of this appeal relates to the integration of
electronic elements on a backside or second side of a die, which is opposite
1 This decision makes reference to the Specification filed September 27,
2014 ("Spec."), the Final Office Action dated August 10, 2016 ("Final
Act."), the Appeal Brief filed November 28, 2016 ("App. Br."), the
Examiner's Answer dated February 10, 2017 ("Ans."), and the Reply Brief
filed April 9, 2017 ("Reply Br.").
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Application 14/499,151
to an active or first side of the die. Spec. i-f 1. Claim 1 is illustrative
(disputed elements italicized):
1. A semiconductor device comprising:
a first semiconductor die with a die substrate, the die
substrate comprising a first side and a second side opposite to the
first side;
a first set of electronic elements integrated on the first side
of the die substrate, wherein the first set of electronic elements
comprise one or more of transistors or active circuit elements;
a second set of electronic elements integrated on the
second side of the die substrate, wherein the second set of
electronic elements comprise one or more of input/ output
devices, thin-film transistors (TFT), passive circuit elements, or
electronic elements for electrostatic discharge (ESD) protection
of the semiconductor device; and
one or more through-substrate vias through the die
substrate configured to couple one or more of the first set of
electronic elements and one or more of the second set of
electronic elements.
App. Br. 12 (Claims Appendix).
The Examiner maintains, and Appellant2 appeals, the following
rejections:
1. Claims 1, 5, 11, 12, 16, and 22 under 35 U.S.C. § 102(a)(l) as
anticipated by Chen; 3
2. Claims 4 and 15 under 35 U.S.C. § 103 as unpatentable over Chen
in view of Hara; 4
2 The Appellant is the Applicant, Qualcomm Incorporated, which is also
identified as the real party in interest. App. Br. 3.
3 Chen et al., US 2014/0103488 Al, published Apr. 17, 2014 ("Chen").
4 Hara et al., US 2003/0197222 Al, published Oct. 23, 2003 ("Hara").
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3. Claims 6-9, 17-20, and 23 under 35 U.S.C. § 103 as unpatentable
over Chen in view of Kamezos; 5 and
4. Claims 10 and 21under35 U.S.C. § 103 as unpatentable over
Chen; and
5. Claims 24 and 25 under 35 U.S.C. § 103 as unpatentable over
Chen in view of Bielen. 6
Ans. 2; App. Br. 5-10; Final Act. 2-10.
OPINION
After review of the arguments and evidence presented by both
Appellant and the Examiner, we affirm the stated rejections for the reasons
provided in the Final Action and Answer. We add the following primarily
for emphasis.
Rejection 1: Anticipation by Chen
It is the Examiner's position that claims 1, 5, 11, 12, 16, and 22 are
anticipated by Chen for the reasons stated on pages 2--4 of the Final Action.
In the Appeal Brief, Appellant argues the subject matter of claims 1,
5, 11, 12, 16, and 22 as a group. In accordance with 37 C.F.R.
§ 41.37(c)(l)(iv), claims 5, 11, 12, 16, and 22 will stand or fall together with
claim 1.
Appellant contends that the Examiner erred because Chen discloses a
plurality of Package-On-Package (POP) structures and "equating a
semiconductor package to a semiconductor die is incorrect." App. Br. 5---6.
5 Kamezos, US 2008/0220563 Al, published Sept. 11, 2008 ("Kamezos").
6 Bielen, US 2010/0059879 Al, published Mar. 11, 2010 ("Bielen").
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According to Appellant, Chen's element 52 of Figure 9 is a dielectric layer
and not a semiconductor die substrate with two sides as required by claim 1.
Id. at 6. Appellant contends that the Examiner erred in not providing any
documentary evidence to support the finding that "a widely accepted
definition for substrate is the physical material upon which a semiconductor
device, e.g., a photovoltaic cell or an integrated circuit, is applied" and that
Chen's layer 52 meets this definition. Id.
Appellant further asserts that Chen's elements 5 8 and 60 are not
electronic elements "integrated in the dielectric layer 52, which the
Examiner regards as a die substrate," because they are "'package
components' which are 'bonded to package 48. "' Id. at 7. Appellants
further argue that paragraph 17 of Chen contradicts the Examiner's finding
that components 58 and 60 are integrated on the layer and that the
attachment of components 58 and 60 by means of solder balls to the
dielectric layer 52 does not read on "second set of electronic elements
integrated on the second side of the die substrate" as recited in claim 1. Id.
at 8.
Finally, Appellant contends that Chen's redistribution lines (RDLs),
element 54, "are clearly not through-substrate vias" as required by claim 1
and do not couple elements 58 and 60 to elements 24 and 25. Id. at 8.
According to Appellant, because Chen's solder ball separates element 58
from the dielectric layer 52 comprising the RDL 54, element 58 is not
integrated on the dielectric layer 52 and the combination of the solder ball
and the RDL does not read on the claimed through-substrate vias. Id.
In response, the Examiner finds that the term "substrate is defined as a
substance or layer that underlies something." Ans. 3 (citing the Merriam-
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Webster dictionary). The Examiner further finds that "[a] die in the
semiconductor art is known as a broad term that defines a substrate, wafer or
layer of material that is used for device fabrication." Id. at 2. The Examiner
also responds that Chen's disclosure of package-on-package structures is not
distinct from a semiconductor die because the terms "package" and "die" are
used interchangeably. Id. (citing Ramachandran 7 i-f 6). In addition, the
Examiner finds that items 52, 40, and 64 of Chen's Figure 9 correspond to
items 104, 102, and 106 of Appellant's Figure 1 illustrating the claimed
substrate, first side, and second side, respectively. Id. at 3--4.
Figure 9 of Chen and Figure 1 of the Specification are shown below
side by side.
Fig. 9 FIG :
Figure 9 shows Chen's POP structure 68 including dielectric layer 52,
molding material 40, and molding compound 64, while Figure 1 illustrates
Appellant's semiconductor die structure 100 containing substrate 104, first
side 102, and second side 106. Chen i-f 18; Spec. i-f 28.
The Examiner interprets the recited "first semiconductor die with a
substrate" as containing a substrate and finds that Chen's layer 52 is a
7 Ramachandran et al., US 2016/0013136 Al, published Jan. 14, 2016
(''Ramachandran").
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substrate and that claim 1 does not specify a particular material for the
substrate. Ans. 4--5.
Regarding electronic elements "integrated on the first side of the die
substrate" as claimed, the Examiner interprets "on" to mean "an element or
layer touching or contacting a surface of another element or layer, either
directly or indirectly" and contrasts that with the term "in" that "is known in
the semiconductor art to require the element or layer to be within a surface
of another layer or element, either partially or completely." Id. at 5---6. The
Examiner further determines that the term "integrated" does not limit the
element to being within the layer because the term is well known in the art to
mean "the combination of elements or the uniting or connection of
elements." Id. at 6.
In the Reply Brief, Appellant contends that the Examiner's
interpretation of "die substrate" constitutes reversible error because the
Examiner's cited portion of Ramachandran "does not indicate[] a die and a
package are interchangeable" but, rather, "that a die or a package may be
coupled to the top of a bare die" and that "a plurality of dies or a die stack
may be included in a package." Reply Br. 2. 8 Appellant additionally cites
Chen2 9 in support of a package being distinguishable from a die. Id. at 3.
Regarding the definition of "substrate," Appellant argues that the
Examiner's definition at best applies to Chen's layers 52 and 64, but not the
combination of multiple layers 40, 52, and 64 because layer 64 does not
appear to lie underneath anything else in Chen. Id. Appellant also argues
8 We note that page numbering only occurs on the first page of Appellant's
Reply Brief. Citations to the Reply Brief herein are sequential from the first
numbered page.
9 Chen et al., US 2014/0091471 Al, published April 3, 2014 ("Chen2") i-f 3.
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that Chen's element 52 is not a semiconductor die substrate with two sides
as claimed because Chen lacks an example material such as silicon in its list
of materials for dielectric layer 52. Id. at 4.
Regarding the claim term "integrated," Appellant argues that the
Examiner's definition of "integrated" does not cover being "stacked on." Id.
at 5. Appellant also contends that the Examiner did not address the
argument that Chen teaches it's package component 58 is a device die, and
package components 60 are discrete passive devices, which are not
integrated on same chips as active devices such as transistors, therefore
bonding packages components 58/60 by means of solder balls to dielectric
layer 52 does not read on the term "integrated." Id.
Regarding substrate vias, Appellant contends that Chen's solder balls
62 cannot be through dielectric layer 54 because they are outside and bonded
to the dielectric layer 54. Id. at 6. According to Appellant, Chen's elements
54 (RDLs formed in the dielectric layer) do not couple elements 58/60 to
elements 24/25 and, therefore, do not teach "configured to couple one or
more of the first set of electronic elements and one or more of the second set
of electronic elements" as recited in Claim 1. Id.
We are not persuaded of reversible error in the Examiner's rejection
of claim 1 as anticipated by Chen based on the cited record on appeal.
Appellant has not provided evidence sufficient to show a patentable
difference in structure between the device of claim 1 and that disclosed by
the prior art. Although Appellant's evidence and arguments attempt to
differentiate package-on-package structures from a die substrate on the basis
that a package includes multiple dies, we agree with the Examiner (Ans. 2)
that "die substrate" as used in claim 1 does not preclude a package absent a
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specific definition. Appellant does not dispute the Examiner's definition of
"substrate" or provide an alternative definition, instead, Appellant argues
(App. Br. 6) that the Examiner's definition is not supported with
documentary evidence. The dictionary definition of "substrate" provided by
the Examiner (Ans. 3), however, also is not disputed by Appellant, but,
rather, Appellant's position (Reply Br. 3) is that it applies only to layers 52
and 64 of Chen, but not the combination of layers 40, 52, and 64.
The difficulty with Appellant's arguments is that Appellant is in
agreement with the Examiner that Chen's layer 52 meets the definition of
substrate as the Examiner finds that Chen's layer 52 underlies a first side
(40) and overlies a second side (64). Ans. 3. The Examiner's finding is
supported by the record. Chen Fig. 9. In addition, the Examiner's position
is supported by Appellant's Figure 1, which corresponds to the arrangement
of Chen's layers 40/52/64 as Appellant's substrate 104 underlies a first side
(102) and overlies a second side (106). Appellant does not persuasively
rebut the Examiner's finding of correspondence between elements
102/104/106 in Appellant's Figure 1 and elements 40/52/64 in Chen's
Figure 9.
Regarding whether Chen teaches that it's dielectric layer 52 is made
of a material typical for semiconductor die substrates (App. Br. 6-7), as the
Examiner notes (Ans. 5), claim 1 does not require a specific material for the
die substrate.
Regarding Appellant's argument that Chen's elements 24, 25 in
Figure 9 are "device dies" not "electronic elements" and that they are "not
integrated in the dielectric layer 52" as required by claim 1 (App. Br. 7), we
are not persuaded that "integrated on ... the die substrate" means that the
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elements must be in the substrate rather than on the substrate. The Examiner
correctly finds that claim 1 recites "on" rather than "in" (Ans. 5-7). The
Examiner's finding that the term "integrated" likewise does not limit the
element to being within the layer is supported by the dictionary definitions
provided "to unite with something else" and "to incorporate into a larger
unit." Ans. 6. The Examiner's finding (Ans. 6) that Chen's elements 24, 25
are active circuit elements and contain transistors is also supported by the
record. Chen i-f 8.
Regarding Appellant's argument that Chen's elements 58 and 60 are
not electronic elements because element 60 is a passive device, which is not
integrated on the same chips as active devices (App. Br. 8; Reply Br. 5),
Appellant's argument is not supported by the record. Paragraph 1 7 of Chen
states "[p ]ackage components 58 and 60 may be packages, device dies,
passive devices, and/or the like." The statement that follows, which
Appellant quotes as support, begins "[i]n some exemplary embodiments"
and, therefore, does not preclude elements 5 8 and 60 from being a device die
as stated in the preceding statement. Appellant's additional argument that
Chen's elements 5 8 and 60 are not integrated on the second side of the die
substrate because they are attached by solder balls to dielectric layer 52 is
not persuasive because the broadest reasonable interpretation of "integrated
on" consistent with the Specification as discussed above means united or
connected with the substrate. Solder balls bond or connect elements 58 and
60 to layer 52. Chen i-fi-1 17, 18.
Similarly, Appellant's argument that Chen's RDLs are not through-
substrate vias connecting elements 58 and 60 to elements 24 and 25 because
element 58 is separated from dielectric layer 52 by a solder ball (App. Br. 8;
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Reply Br. 6) is not persuasive because the solder ball "couples" element 58
through the layers of RD Ls to the top surface of element 25 as the Examiner
finds (Ans. 8; Chen Fig. 9). Appellant's assertion that because solder balls
62 are "outside and bonded to the dielectric layer 54 [sic], [they] cannot also
be through the dielectric layer 54 [sic]" (Reply Br. 8) is not supported by the
record cited in this appeal. Chen's element 54 are RDLs formed in dielectric
layer 52. Chen i-f 16. Thus, Chen's element 54 is "through the dielectric
layer" which is element 52. To the extent that Appellant's argument seeks
to limit the term "couple" recited in claim 1 to mean directly contacts
without any intervening connectors, Appellant has not provided a basis for
such an interpretation to distinguish the cited prior art.
Accordingly, we affirm the stated rejection of claim 1 as anticipated
by Chen.
Rejections 2-5: Obviousness over Chen and Additional References
It is the Examiner's position that Chen alone or in combination with
secondary references suggests the subject matter of claims 4, 6-10, 15, 17-
21, and 23-25 for the reasons stated on pages 4--10 of the Final Action.
Appellant separately argues claim 10 on pages 6-7 of the Appeal
Brief. Appellant contends that the Examiner has not shown that Chen's
dielectric layer 52 is made of a material inclusive of silicon (Appellant's
claim 10 recites "the die substrate is made of silicon") because Chen states
"dielectric layers 52 are formed of dielectric materials such as oxides,
nitrides, carbides, carbon nitrides, combinations thereof' which are not
recited in claim 10. App. Br. 6-7. Regarding the material of the substrate
specified in claim 10, the Examiner finds that silicon oxides, nitrides, and
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carbides are well-known in the art, readily used as both substrate materials
and dielectric materials, and determines it would have been obvious in view
of Chen's teaching of forming the layer of oxides, nitrides, and carbides. Id.
at 5 (citing Chen i-f 16). In the Reply Brief, Appellant argues that the
Examiner's finding that silicon oxides, nitrides and carbides are readily used
substrate materials in the semiconductor field is unsupported. Reply Br. 4.
Regarding whether Chen teaches that it's dielectric layer 52 is made
of a material typical for semiconductor die substrates, Appellant does not
dispute the Examiner's finding (Ans. 5) that silicon oxides, nitrides, and
carbides are readily used for both dielectric and substrate materials and
would have been obvious from Chen's disclosure. Appellant also does not
adequately rebut the Examiner's finding (Final Act. 8) that silicon is a
common material for "oxides, nitrides and carbides" which Chen discloses
for use in element 52. Silicon oxides, nitrides, and carbides are "made of
silicon" as recited in claim 10. Therefore, we are not persuaded by
Appellant's insinuation (App. Br. 6) that the lack of an explicit disclosure of
silicon in Chen indicates that element 52 is not a die substrate as required by
claim 1 from which claim 10 depends.
Appellant also argues the subject matter of claims 4, 6-10, 15, 17-21,
and 23-25 as a group, asserting that the supplementary references Hara,
Kamezos, and Bielen do not cure the deficiencies of Chen as discussed in
connection with claim 1. App. Br. 9-10.
Because we find that Chen is not deficient in terms of disclosing the
"die substrate," "electronic elements integrated on" the first and second side
of the die substrate, and the "through-substrate vias" required by
independent claim 1 for the reasons discussed above, we likewise affirm the
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Examiner's decision to reject dependent claims 4, 6-10, 15, 17-21, and 23-
25 under 35 U.S.C. § 103(a) over Chen alone or in combination with
supplemental references.
DECISION
For the foregoing reasons, we affirm all of the Examiner's rejections
under 35 U.S.C. §§ 102(a)(l) and 103.
TIME PERIOD FOR RESPONSE
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(l).
ORDER
AFFIRMED
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