Ex Parte Rajasekaran et al

Patent Trial and Appeal Board

Jan 30, 2017

13741465 (P.T.A.B. Jan. 30, 2017)

United States Patent and Trademark Office
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
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Alexandria, Virginia 22313-1450
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APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
13/741,465 01/15/2013 Jeevanandham Rajasekaran 5887-388 1012
144016 7590 02/01/2017
SheriHan Rnsis; P P
EXAMINER
1560 Broadway, Suite 1200
Denver, CO 80202
DOAN, DUC T
ART UNIT PAPER NUMBER
2135
NOTIFICATION DATE DELIVERY MODE
02/01/2017 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
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PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte JEEVANANDHAM RAJASEKARAN and ANKIT SIHARE
Appeal 2016-005864
Application 13/741,4651
Technology Center 2100
Before MAHSHID D. SAADAT, THU A. DANG, and
SCOTT B. HOWARD, Administrative Patent Judges.
HOWARD, Administrative Patent Judge.
DECISION ON APPEAL
Appellants appeal under 35 U.S.C. § 134(a) from the Examiner’s
Final Rejection of claims 1—20, which constitute all of the claims pending in
this application. We have jurisdiction under 35 U.S.C. § 6(b).
We affirm.
1 Appellants identify Avago Technologies General IP (Singapore) Pte. Ltd.
(“Avago”) as the real party in interest. Br. 3.
Appeal 2016-005864
Application 13/741,465
THE INVENTION
The disclosed invention is directed “to systems and techniques for
improving write cliff handling in cache based storage controllers.” Spec.
11-
Claim 1, reproduced below with the disputed limitations italicized, is
illustrative of the claimed subject matter:
1. A system for continuously writing to a secondary storage
cache, the system comprising:
a processor configured to divide a data storage region of a
secondary storage cache into a first cache region and a second
cache region and determine a data storage threshold for the first
cache region; and
a memory configured to store the data storage threshold
for the first cache region, the memory having computer
executable instructions stored thereon, the computer executable
instructions configured for execution by the processor to:
write data to the first cache region until the data
storage threshold is met, and
in response to meeting the data storage threshold for
the first cache region, write additional data to the second
cache region while writing back the data stored in the first
cache region to a primary storage device.
REFERENCES
The prior art relied upon by the Examiner as evidence in rejecting the
claims on appeal is:
Conley et al. (“Conley”) US 2005/0195635 A1 Sept. 8, 2005
Basso et al. (“Basso”) US 2006/0039376 Al Feb. 23, 2006
REJECTIONS
Claims 1, 2, 5—9, 12—16, 19, and 20 stand rejected under pre-AIA 35
U.S.C. § 103(a) as being unpatentable over Conley. Final Act. 2—7, 13—14.
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Claims 3,4, 10, 11, 17, and 18 stand rejected under pre-AIA 35
U.S.C. § 103(a) as being unpatentable over Conley in view of Basso. Final
Act. 7-10.
ANALYSIS
We have reviewed the Examiner’s rejection in light of Appellants’
arguments that the Examiner erred. In reaching this decision, we have
considered all evidence presented and all arguments made by Appellants.
We are not persuaded by Appellants’ arguments regarding claims 1—20.
Claims 1—13, 15—20
Appellants argue the Examiner erred in finding Conley teaches the
disputed claim limitations. Br. 5—11. Specifically, Appellants argue Conley
“is silent regarding the concept of different partitions of the cache interacting
with each other in the manner described in claim 1. For example, Conley
describes no actions at one partition that are triggered by the status of
another partition.” Br. 6.
The Examiner finds Conley teaches “writing] data to the first cache
region until the data storage threshold is met, and in response to meeting the
data storage threshold for the first cache region, write additional data to the
second cache region while writing back the data stored in the first cache
region to a primary storage device.” Final Act. 3 (citing Conley Figs. 2, 9—
11,33—38, and 54—59); see also Final Act. 14 (“When data fills up the
first portion (i.e. claimed threshold), data continues to fill the second portion
while simultaneously write data from the first portion to NVM storage.
Thus Examiner submits that Conley disclosure of write stream data in write-
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though buffered / cached clearly teaches the limitations as being recited in
the claims.”); Ans. 15—16. The Examiner further finds “the cache is divided
to portions so that while data is received in the second portion the data in the
first portion is written back to storage” and that “the amount of data stored
the first portion triggers the data stream to write to the second portion while
the cache writes back data of the first portion, and therefor teaches the
claimed ‘meeting the threshold of a region.’” Ans. 15—16 (citing Conley
154).
Our reviewing court guides that “the question under 35 USC § 103 is
not merely what the references expressly teach but what they would have
suggested to one of ordinary skill in the art at the time the invention was
made.” Merck & Co., Inc. v. Biocraft Laboratories, Inc., 874 F.2d 804,
807-08 (Fed. Cir. 1989). Moreover, “[ejvery patent application and
reference relies to some extent upon knowledge of persons skilled in the art
to complement that [which is] disclosed. . . .” In re Bode, 550 F.2d 656, 660
(CCPA 1977) (quoting In re Wiggins, 488 F.2d 538, 543 (CCPA 1973)).
Those persons “must be presumed to know something” about the art “apart
from what the references disclose.” In re Jacoby, 309 F.2d 513, 516 (CCPA
1962). Additionally, the skilled artisan is “[a] person of ordinary creativity,
not an automaton.” KSRInt’l Co. v. Teleflex Inc., 550 U.S. 398, 421 (2007).
Furthermore, there is no requirement in an obviousness analysis for the prior
art to “contain a description of the subject matter of the appealed claim in
ipsissimis verbis.” In re May, 574 F.2d 1082, 1090 (CCPA 1978).
We agree with and adopt the Examiner’s finding that Conley, at a
minimum, suggests the disputed claim limitation. Conley teaches using
either a buffer cache or a partitioned buffer cache. Conley ^fl[ 33 (discussing
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a buffer cache), 35 (discussing a partitioned buffered cache), 54 (stating that
either the buffered cache or partitioned buffered cache could be used).
Conley further suggests that once a portion of the cache reaches a threshold
(sufficient data to allow a full metapage to be programmed) it will write
back the data and allow other portions to receive data from the host in order
to increase speed by taking advantage of parallelism:
In the NVM, the data may be kept in data cache and programmed
when required. By returning a signal to a host indicating that the
data is written to NVM, when in fact it is not in NVM but in
write-through cache, the apparent time to store data may be
shortened. This allows the host to send subsequent data more
rapidly. More data may be sent by the host without waiting for
the previous data to be programmed into NVM. A memory card
may transfer a first portion of data from write-through cache to
NVM while simultaneously transferring a second portion of data
from a host into write-through cache. A write-through cache
may allow more efficient programming of the NVM. Sectors of
data may be stored in write-through cache until enough data
has been transferred by the host to allow a full metapage to be
programmed using the maximum parallelism of the NVM
array. This may allow programming to occur more rapidly
because of increased parallelism and may further improve
performance by reducing or avoiding any garbage collection
required after programming.
Conley 1 54 (emphasis added). Accordingly, we are not persuaded by
Appellants’ argument that the Examiner erred.
Appellants also argue that there are three “further notable differences
between Conley and claim 1.” Br. 6. First, Appellants argue that Conley
paragraphs 54—59 describe write through, not write back, operations and that
“[a] write through cache for example synchronously writes to the cache and
immediately flushes the newly cached data to persistent storage .... In
contrast, a write back cache operates for example by writing to cache, and
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waiting (e.g., for further I/O) before flushing that cache data to persistent
storage.” Br. 6. Accordingly to Appellants, claim 1 is directed to write
back, not write through operations. See Br. 6—7.
Second, Appellants argue that “the operations for each cache
region/partition in Conley (even the write through one) are performed
independently of other cache regions/partitions” and that “there is not [a]
storage threshold to meet in order to flush data because the cache is
constantly operating in a write-through mode where any incoming I/O is
flushed as soon as possible.” Br. 7—8.
Third, Appellants argue “the cited portions of Conley never discuss a
storage threshold as a trigger that causes: writing back from one region of a
cache while writing additional data to another region of the same cache.”
Br. 9-10.
With regard to the first point, Appellants do not accurately describe
the difference between a write-through cache policy and a write-back cache
policy. As Conley makes clear, the difference between the two is not
whether or not the data is flushed immediately; instead the difference is
whether the data can be modified when in the buffer cache:
A write-through cache policy stores data in buffer cache and
subsequently writes the data to the memory array, without
modifying the data. A write-back cache policy stores data in
buffer cache and may modify the data in buffer cache without
writing the data to the memory array.
Conley 117; see also Conley 1 54 (describing how a write-through cache
can be implemented to keep data stored in the buffer cache until a threshold
has been met).
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Additionally, the Examiner concludes that claim 1 merely requires
“writing back of data in a cache memory” and that “the writing back of data
in a cache is not the same as describing operation(s) of a write-back cache.”
Ans. 16 (emphasis omitted).
During prosecution, claims must be given their broadest reasonable
interpretation while reading claim language in light of the specification as it
would be interpreted by one of ordinary skill in the art. In re Am. Acad, of
Sci. Tech. Ctr., 367 F.3d 1359, 1364 (Fed. Cir. 2004). Under this standard,
we interpret claim terms using “the broadest reasonable meaning of the
words in their ordinary usage as they would be understood by one of
ordinary skill in the art, taking into account whatever enlightenment by way
of definitions or otherwise that may be afforded by the written description
contained in the applicant’s specification.” In re Morris, 127 F.3d 1048,
1054 (Fed. Cir. 1997).
Claim 1 recites “writing back the data stored in the first cache region
to a primary storage device.” Br. 12 (Claims App’x). Although claim 1
requires data to be written back to the primary storage device, there is no
limitation on the type of cache used for the temporary storage. Accordingly,
we agree with the Examiner that under the broadest reasonable construction
of the claim, the claim limitations are broad enough to encompass either a
write-back cache or a write-through cache. That construction is consistent
with ordinary meaning of the words of the claims, which only recite “writing
back the data” without specifying the type of cache used. The construction
is also consistent with the Specification, which merely describes writing the
data without specifying the type of cache used. See Spec. ]Hf 11, 13.
Because Appellants’ arguments are not commensurate with the scope of the
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claims, they are unpersuasive. See In re Self, 671 F.2d 1344, 1348 (CCPA
1982).
With regard to the second and third points, we previously found
(pages 4—5, supra) that Conley teaches to suggests using a storage threshold
that triggers writing back from one region while at the same time writing
additional data to another region of the same cache.2 Therefore, we are not
persuaded by Appellants’ arguments.
Accordingly, we sustain the Examiner’s rejection of claim 1, along
with claims 8 and 15, which are argued on the same grounds, and dependent
claims 2—7, 9—13, and 16—20, which are not argued separately. See Br. 10-
11.
Claim 14
Appellants argue the Examiner erred in finding Conley teaches the
switching back and forth claimed in dependent claim 14. Br. 11. More
particularly, Appellants argue “Conley does not describe the additional step
of returning to write data to the first cache region in combination with
detecting that the second cache region has reached a second data storage
threshold.” Id. Appellants provide two example in support of their
argument:
For example, if the cache of Conley were arbitrarily divided into
two regions, there would be spillover as the system wrote to and
flushed from both regions without paying any attention to the
cache boundaries. On the other hand, if the cache of Conley were
2 Additionally, to the extent Appellants rely on Conley paragraphs 11—13 to
support their arguments, Appellants’ argument is not persuasive because
those paragraphs describe the prior art, not the Conley invention. See
Conley 1—13 (background section).
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Application 13/741,465
divided into thousands of regions, then flushing would not move
back and forth between the same two regions over and over.
Br. 11.
The Examiner finds Conley teaches “determining a second data
storage threshold for the second cache region; storing the additional data in
the second cache region until the second data storage threshold is met; and
storing data in the first cache region while writing back the additional data
stored in the second cache region to the primary storage device.” Final Act.
5.
We are not persuaded of Examiner error because Appellants do not
provide persuasive argument or evidence to support the assertion. Instead,
Appellants’ argue the alleged operation of Conley without providing any
support, such as a declaration or citation to Conley itself. It is well settled
that mere attorney arguments and conclusory statements, which are
unsupported by factual evidence, are entitled to little probative value. In re
Geisler, 116 F.3d 1465, 1470 (Fed. Cir. 1997); see also In re Pearson, 494
F.2d 1399, 1405 (CCPA 1974) (attorney argument is not evidence). Instead,
we agree with and adopt the Examiner’s finding that Conley teaches or
suggests the additional limitations of claim 14.
Accordingly, we sustain the Examiner’s rejection of claim 14.
DECISION
For the above reasons, we affirm the Examiner’s decisions rejecting
claims 1—20.
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No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(l)(iv). See 37
C.F.R. § 41.50(f).
AFFIRMED
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