Ex Parte Masumoto

Patent Trial and Appeal Board

Sep 25, 2018

14320825 (P.T.A.B. Sep. 25, 2018)

UNITED STA TES p A TENT AND TRADEMARK OFFICE
APPLICATION NO. FILING DATE
14/320,825 07/01/2014
23494 7590 09/27/2018
TEXAS INSTRUMENTS IN CORPORA TED
PO BOX 655474, MIS 3999
DALLAS, TX 75265
UNITED ST A TES OF AMERICA
FIRST NAMED INVENTOR
Mutsumi Masumoto
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www .uspto.gov
ATTORNEY DOCKET NO. CONFIRMATION NO.
TI-74235 5373
EXAMINER
HAN, JONATHAN
ART UNIT PAPER NUMBER
2818
NOTIFICATION DATE DELIVERY MODE
09/27/2018 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
uspto@ti.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte MUTSUMI MASUMOTO
Appeal2018-000773
Application 14/320,825
Technology Center 2800
Before BRADLEY R. GARRIS, LINDA M. GAUDETTE, and
MERRELL C. CASHION, JR., Administrative Patent Judges.
CASHION, Administrative Patent Judge.
DECISION ON APPEAL
STATEMENT OF THE CASE
This is an appeal under 35 U.S.C. § 134 from a Final Rejection of
claims 1-3 and 10-15. We have jurisdiction under 35 U.S.C. § 6.
We AFFIRM.
Appeal2018-000773
Application 14/320,825
Claim 1 is illustrative of the subject matter on appeal and is
reproduced below:
1. A method for fabricating packaged semiconductor
devices in panel format, comprising:
providing a flat panel sheet as a carrier including a
substrate of an insulating plate, and a tape having a surface
layer of a first adhesive, a core base film, and a bottom layer
with a second adhesive, the bottom layer attached to the
substrate;
attaching a set of contiguous semiconductor chips onto
the first adhesive layer, the set of contiguous semiconductor
chips forming a rectangle with sidewalls, terminals of the set of
contiguous semiconductor chips having metal bumps facing
away from the first adhesive layer;
laminating using an insulating material to cover the metal
bumps;
grinding the insulating material until the tops of the metal
bumps are exposed;
plasma-cleaning and cooling the panel and set of
contiguous semiconductor chips; and
sputtering at least one layer of metal onto the exposed
portions of the insulating material and metal bumps.
Appellant1 (see generally App. Br.) requests review of the following
rejections from the Examiner's Final Office Action:
(a) claims 1, 10, 12, 14, and 15 rejected under 35 U.S.C. § 103 as
unpatentable over Oh (US 2011/0037165 Al, published February 17, 2011)
and Noguchi (US 2002/0055255 Al, published May 9, 2002);
1 Texas Instruments Incorporated is the Applicant/ Appellant and identified
as the real party in interest. App. Br. 3.
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Application 14/320,825
(b) claims 2 and 3 rejected under 35 U.S.C. § 103 as unpatentable
over Oh, Noguchi, and Bhattacharya (US 4,463,059, issued July 31, 1984);
and
(c) claims 11 and 13 rejected under 35 U.S.C. § 103 as unpatentable
over Oh, Noguchi, and Chi (US 2011/0291249 Al, published December 1,
2011).
Appellant presents arguments for claim 1 and relies on these
arguments to address the patentability of claims 10, 12, 14, and 15 as well as
separately rejected claims 2, 3, 11, and 13. See generally App. Br.
Accordingly, we select claim 1 as representative of the subject matter before
us for review on appeal and decide the appeal as to all grounds of rejection
based on the arguments made by Appellant in support of patentability of
claim 1.
OPINION
After review of the respective positions provided by Appellant and the
Examiner, we AFFIRM the Examiner's prior art rejections of claims 1-3
and 10-15 for the reasons presented by the Examiner. Our reasoning
follows.
Claim 1
Independent claim 1 is directed to a method for fabricating packaged
semiconductor devices in panel format where a set of contiguous
semiconductor chips is attached onto the first adhesive layer of a flat panel
carrier sheet.
We refer to the Examiner's Final Action for a statement of rejection
for claim 1. Final Act. 3--4.
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Application 14/320,825
The rejection turns on the meaning of the claim term "contiguous
semiconductor chips." Appellant argues that the disputed term means that
the semiconductor chips are physically touching and are connected
throughout in an unbroken sequence. App. Br. 7. In support of this
argument, Appellant directs us to the Specification describing the
"contiguous semiconductor integrated circuit chips arranged as a unit, i.e.,
four chips fabricated in single-crystalline silicon and not yet singulated."
App. Br. 6; Spec. ,r 21. Singulating, in the context of the Specification,
means separating the contiguous chips into discrete devices at the end of the
fabrication process. Spec. ,r 34.
Appellant argues that Oh, even as modified by Noguchi, fails to show,
teach, or suggest the claimed feature of the contiguous semiconductor chips
because Oh teaches semiconductor chips that have been singulated and
individually placed on separated heated spreaders. App. Br. 6. Appellant
further contends that the Examiner's definition that "dies arranged in a
sequence ... can be considered a set of contiguous chips" is inconsistent
with a broadest reasonable interpretation of the argued claim language,
which Appellant asserts is that "contiguous semiconductor integrated circuit
chips arranged as a unit, i.e., four chips fabricated in single-crystalline
silicon and not yet singulated." App. Br. 6; see Spec. ,r 21.
We are unpersuaded by these arguments for the reasons presented by
the Examiner. "[D]uring examination proceedings, claims are given their
broadest reasonable interpretation consistent with the specification." In re
Translogic Tech., Inc., 504 F.3d 1249, 1256 (Fed. Cir. 2007) (quoting In re
Hyatt, 211 F.3d 1367, 1372 (Fed. Cir. 2000)). See also In re Am. Acad. of
Sci. Tech Ctr., 367 F.3d 1359, 1364 (Fed. Cir. 2004) (explaining that the
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Appeal2018-000773
Application 14/320,825
scope of the claims in patent applications is not determined solely on the
basis of the claim language, but upon giving claims their broadest reasonable
construction in light of the specification as it would be interpreted by one of
ordinary skill in the art); Phillips v. AWH Corp., 415 F.3d 1303, 1315 (Fed.
Cir. 2005) ("[T]he specification 'is always highly relevant to the claim
construction analysis. Usually, it is dispositive; it is the single best guide to
the meaning of a disputed term."' ( citation omitted)). In general,
the PTO applies to the verbiage of the proposed claims the
broadest reasonable meaning of the words in their ordinary
usage as they would be understood by one of ordinary skill in
the art, taking into account whatever enlightenment by way of
definitions or otherwise that may be afforded by the written
description contained in the [Appellant's] [S]pecification.
In re Morris, 127 F.3d 1048, 1054 (Fed. Cir. 1997).
In this case, Appellant does not direct us to specific definition for
either of the terms "contiguous" or "contiguous semiconductor chips" in the
Specification. The Examiner, in tum, determines that the broadest
reasonable meaning of "contiguous" does not require physical contact as
asserted by Appellant. Ans. 7-8. The Examiner points to definitions in
three different dictionaries that support an interpretation of "contiguous" as
requiring close proximity, but not physical contact. Id. at 7-8. Based on
these definitions, the Examiner concludes that Oh's semiconductor chips are
contiguously arranged. Id. at 8.
While Appellant points to paragraph 21 of the Specification to assert
that the term "contiguous" requires the chips to be in physical contact, this
portion of the Specification only addresses an exemplary embodiment of the
disclosed invention. Having reviewed the Specification in its entirety, we do
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Application 14/320,825
not find any language that supports an interpretation of the claims as limited
to the embodiment described in paragraph 21 of the Specification. See
SuperGuide Corp. v. DirecTV Enter., Inc., 358 F.3d 870, 875 (Fed. Cir.
2004) ("Though understanding the claim language may be aided by the
explanations contained in the written description, it is important not to
import into a claim limitations that are not a part of the claim. For example,
a particular embodiment appearing in the written description may not be
read into a claim when the claim language is broader than the
embodiment."). Nor does Appellant provide persuasive evidence to support
a more narrow interpretation of the claim term "contiguous."
While Appellant argues Oh's semiconductor chips are not contiguous
because they have been singulated, App. Br. 6, the portions of Oh relied
upon by the Examiner relate to the initial stages of fabrication, i.e., prior to
singulation.
Therefore, Appellant has not identified error in the Examiner's
determination of obviousness. Accordingly, we affirm the Examiner's prior
art rejections of claims 1-3 and 10-15 under 35 U.S.C. § 103(a) for the
reasons presented by the Examiner and given above.
ORDER
The Examiner's prior art rejections of claims 1-3 and 10-15 under
35 U.S.C. § 103(a) are affirmed.
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TIME PERIOD
No time period for taking any subsequent action in connection with
this appeal maybe extended under 37 C.F.R. § 1.I36(a)(l).
AFFIRMED
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