Ex Parte Kwon et al

Patent Trial and Appeal Board

May 31, 2017

12407949 (P.T.A.B. May. 31, 2017)

United States Patent and Trademark Office
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O.Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
12/407,949 03/20/2009 ChoongHwan Kwon 2515.0169 8324
112165 7590 06/02/2017
STATS ChipPAC/PATENT LAW GROUP:
Atkins and Associates, P.C.
55 N. Arizona Place, Suite 104
Chandler, AZ 85225
EXAMINER
SALERNO, SARAH KATE
ART UNIT PAPER NUMBER
2814
NOTIFICATION DATE DELIVERY MODE
06/02/2017 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
main@plgaz.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte CHOONGHWAN KWON,
SOOMOON PARK, and HEEJO CHI
Appeal 2016-003744
Application 12/407,949
Technology Center 2800
Before JEFFREY T. SMITH, MARKNAGUMO, and
MICHAEL P. COLAIANNI, Administrative Patent Judges.
COLAIANNI, Administrative Patent Judge.
DECISION ON APPEAL
Appeal 2016-003744
Application 12/407,949
Appellants1 appeal under 35 U.S.C. § 134 the Final Rejection of
claims 5—19, 25—33, and 35—38. We have jurisdiction over the appeal
pursuant to 35 U.S.C. § 6(b).
We AFFIRM.
Appellants’ invention is directed to methods of forming a conformal
solder wet-enhancement layer on a bump-on-lead site (Spec. 11).
Claim 5 is illustrative:
5. A method of making a semiconductor device,
comprising:
providing a substrate;
forming a first conductive layer including first and
second portions which are electrically isolated during formation
of the first conductive layer over a surface of the substrate;
forming an insulating layer over the first conductive layer
and substrate;
forming an opening in the insulating layer over the first
conductive layer and the surface of the substrate;
forming a second conductive layer over the surface of the
substrate and the first conductive layer within the opening in
the insulating layer; and
testing for electrical continuity between the first and
second portions of the first conductive layer.
Appellants appeal the following rejections:
1. Claims 5, 12, 25, 29, 30, 35, and 36 are rejected under 35 U.S.C.
§ 102(b) as unpatentable over Liu (US 6,358,831 Bl, Mar. 19,
2002).
1 Appellants identify STATS ChipPAC, Ltd., as the real party in interest
(Br. 1).
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Appeal 2016-003744
Application 12/407,949
2. Claims 8—10, 15—17, 26, 27, 33, and 37 are rejected under
35 U.S.C. § 103(a) as unpatentable over Liu in view of Okamoto
(US 6,222,935 Bl, Apr. 24, 2001).
3. Claims 6, 7, 13, 14, 19, 28, 31, 32, and 38 are rejected under
35 U.S.C. § 103(a) as unpatentable over Liu in view of Kainou
(US 2005/0167832 Al, Aug. 4, 2005).
4. Claims 11 and 18 are rejected under 35 U.S.C. § 103(a) as
unpatentable over Liu in view of Yoshida (US 2002/0090831 Al,
July 11,2002).
Appellants present the same arguments for each of independent claims
5, 12, 25, 29, and 35 (Br. 7—20). In accordance with 37 C.F.R.
§ 41.37(c)(l)(iv), we select claim 5 as representative of the claims on which
to render our decision. Appellants’ arguments regarding the claims under
rejections (2) to (4) rely on the same arguments made regarding Liu under
rejection (1). Therefore, the claims under rejections (2) to (4) will stand or
fall with our analysis of the rejection of claim 5 under rejection (1).
FINDINGS OF FACT & ANALYSIS
The Examiner finds that Liu teaches the steps recited in claim 5 (Final
Act. 2—3). The Examiner finds that Liu in column 2 teaches the step of
testing for electrical continuity between the first and second portions of the
first conductive layer (Final Act. 3). The Examiner finds that Liu’s column
2 disclosure of “wafer acceptance testing (WAT) and subsequent package
stress testing” is used to test for unwanted short circuits in the
semiconductor bonds (Ans. 9). The Examiner finds that claim 5 only
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Appeal 2016-003744
Application 12/407,949
requires the act of continuity testing and does not specify whether the
continuity test is used to find an electrical connection or absence thereof
(Ans. 9-10).
Appellants argue that Liu is silent about whether conductive line 50
and bonding pad base segment 54 are actually electrically isolated during
formation (Br. 7). Appellants contend that Liu’s conductive line 50 and
bonding pad 54 may be common in another part of the substrate. Id.
The Examiner finds that Liu teaches that bonding pad 54 and
conductive line 52 are electrically connected together, but Liu does not teach
that line 50 and pad 54 are electrically connected (Ans. 9). The Examiner
finds that Liu’s failure to describe an electrical connection between pad 54
and conductive line 50 implies that pad 54 is electrically isolated from the
line 50 in that layer. Id. Appellants do not respond to or otherwise show
reversible error with this finding of the Examiner. Appellants do not
dispute that Liu teaches all the other steps recited in claim 5 with the
exception of the testing the electrical continuity step (Br. 7-10).
Moreover, the disputed portion of claim 5 recites “forming a first
conductive layer including first and second portions which are electrically
isolated during formation of the first conductive layer over a surface of the
substrate.” Claim 5 does not exclude the first and second portions being
electrically isolated from one another over a section of the first conductive
layer during formation of the layer. For example, Liu’s Figure 3 shows
conductive line 50 separated from bonding pad 54 and conductive line 52
using insulative material 38 would be electrically isolated over the section of
the conductive layer shown in Figure 3 during its formation. Liu’s disclosure
satisfies the requirements of claim 5.
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Appeal 2016-003744
Application 12/407,949
Appellants argue that if Liu’s conductive line 50 and bonding pad
base segment 54 are electrically isolated, then the Liu fails to teach testing
for electrical continuity between the first and second portions of the first
conductive layer (Br. 8). Appellants contend that if Liu’s conductive line 50
and bonding pad 54 were electrically isolated there would have been no
reason to test for electrical continuity between electrically isolated
structures. Id.
Appellants’ argument is not persuasive because the claim does not
require the electrical continuity test to be positive or negative. The
Examiner finds, and Appellants do not dispute, that Liu’s wafer acceptance
testing involves testing for unwanted short-circuits in a circuit. Therefore,
Liu’s wafer acceptance testing would have included testing to ensure that
conductive line 50 and bond pad 54 have the proper electrical continuity.
On this record, we affirm the Examiner’s § 102(b) rejection over Liu.
We also affirm the Examiner’s § 103 rejections (2) to (4) for the same
reasons.
DECISION
The Examiner’s decision is affirmed.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(l)(iv).
AFFIRMED
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