Ex Parte Hutchens et al

Patent Trial and Appeal Board

Feb 19, 2013

10991705 (P.T.A.B. Feb. 19, 2013)

UNITED STATES PATENT AND TRADEMARKOFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
10/991,705 11/18/2004 Chriswell G. Hutchens 063718.0428 8968
7590 02/19/2013
Bradley S. Bowling
Baker Botts L.L.P.
One Shell Plaza
910 Louisiana
Houston, TX 77002-4995
EXAMINER
HUR, JUNG H
ART UNIT PAPER NUMBER
2824
MAIL DATE DELIVERY MODE
02/19/2013 PAPER
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
____________________

BEFORE THE PATENT TRIAL AND APPEAL BOARD
____________________

Ex parte CHRISWELL G. HUTCHENS, ROGER L. SCHULTZ, CHIA-
MING LIU, and JAMES J. FREEMAN
____________________

Appeal 2010-009125
Application 10/991,705
Technology Center 2800
____________________

Before MAHSHID D. SAADAT, DEBRA K. STEPHENS, and JUSTIN
BUSCH, Administrative Patent Judges.

STEPHENS, Administrative Patent Judge.

DECISION ON APPEAL
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Appellants appeal under 35 U.S.C. § 134(a) (2002) from a final
rejection of claims 1, 3, 4, 6-26, 43, 45, 46, 48-65, 125, 129, 131, 135, and
137-144. We have jurisdiction under 35 U.S.C. § 6(b). Claims 2, 5, 27-42,
44, 47, 66-124, 126-128, 130, 132-134, and 136 were cancelled.
We AFFIRM.

Introduction
According to Appellants, the invention relates to a memory system for
storing one or more bits that includes a substrate comprising sapphire or
diamond, a magnetic random access memory (MRAM) array disposed on
the substrate, and a memory controller disposed on the substrate and in
communication with the MRAM array. (Abstract).

STATEMENT OF THE CASE

Exemplary Claims
Claims 1 and 11 are exemplary claims and are reproduced below:
1. A memory system for storing one or more bits, comprising:

a substrate comprising sapphire;

a magnetic random access memory (MRAM) array disposed on
the substrate; and

a memory controller disposed on the substrate and in
communication with the MRAM array, where the memory
controller comprises:

one or more semiconductor devices, where one or
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more of the semiconductor devices comprise:

an active layer having a thickness tSi and
comprising a channel region, the channel region having a
length L, where L/tSi is between 11.8 and 25; and

an oxide layer disposed on the active layer.

11. A memory system for storing one or more bits, comprising:

a substrate comprising sapphire;

a magnetic random access memory (MRAM) array disposed on
the substrate; and

a memory controller disposed on the substrate and in
communication with the MRAM array, where the memory
controller comprises:

one or more P-channel transistors comprising a first portion of
the substrate, where the P-channel semiconductor device is
characterized by a gain ßp and a leakage current IOFF-p; one or
more N-channel transistors in communication with the one or
more P-channel transistors, the N-channel transistors
comprising a second portion of the substrate, where
each N-channel transistor is characterized by a gain ßn and a
leakage current IOFF-N; and where, at a predetermined
temperature:

ßp ≈ ßn; and
IOFF-P ≈ IOFF-N.

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References
Sandhu US 6,358,756 B1 Mar. 19, 2002
Hirai US 2002/0057594 A1 May 16, 2002
Fitzgerald US 2002/0123197 A1 Sep. 5, 2002
Morishita EP 1120818 A1 Aug. 1, 2001
S. Cristoloveanu and G. Reichet, Recent Advances in SOI Materials and
Device Technologies for High Temperature , High-Temperature Electronic
Materials, Devices and Sensors Conference, IEEE 1998 at pp. 86-93.

Bengt Edholm, Lars Vestling, Mats Bergh, Stefan Tiensuu, and Anders
Söderbärg, Silicon-On-Diamond MOS-Transistors with Thermally Grown
Gate Oxide, Proceedings 1997 IEEE Int’l SOI Conference, Oct. 1997 at pp.
30-31.

Mishel Matloubian, Cheng-Eng Daniel Chen, Bor-Yen Mao, Ravishankar
Sundaresan, and Gorgon P. Pollack, Modeling of the Subthreshold
Characteristics of SOI MOSFET’s with Floating Body, IEEE Trans. Electron
Devices, Vol. 37, No. 9 Sept. 1990 at pp. 1985-1990.

Philip G. Neudeck, Robert S. Okojie, and Liang-Yu Chen, High-
Temperature Electronics – A Role for Wide Bandgap Semiconductors?,
Proceedings of the IEEE, Vol. 90., No. 6, June 2002 at pp. 1065-1076.

John P. Uyemura, CMOS Logic Circuit Design, Kluwer, (1999).

Rejections
(1) Claims 1, 3, 4, and 6 stand rejected under 35 U.S.C. § 103(a) as
being unpatentable over Sandhu and Morishita.
(2) Claims 7-10 stand rejected under 35 U.S.C. § 103(a) as being
unpatentable over Sandhu, Morishita, and Cristoloveanu.
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(3) Claims 11, 13-15, 22, 25, and 26 stand rejected under
35 U.S.C. § 103(a) as being unpatentable over Sandhu, Fitzgerald, Uyemura,
and Matloubian.
(4) Claims 16-21 and 138-144 stand rejected under
35 U.S.C. § 103(a) as being unpatentable over Sandhu, Fitzgerald, Uyemura,
Matloubian, and Morishita.
(5) Claims 12, 23, and 24 stand rejected under 35 U.S.C. § 103(a)
as being unpatentable over Sandhu, Fitzgerald, Uyemura, Matloubian, and
Neudeck.
(6) Claims 125 and 129 stand rejected under 35 U.S.C. § 103(a) as
being unpatentable over Sandhu, Morishita, and Neudeck.
(7) Claims 43, 45, 46, 48-65, 131, and 135 stand rejected under
35 U.S.C. § 103(a) as being unpatentable over Sandhu, Morishita,
Fitzgerald, Uyemura, Matloubian, Cristoloveanu, and/or Neudeck, and
Edholm, and Hirai.
(8) Claim 137 stands rejected under 35 U.S.C. § 103(a) as being
unpatentable over Sandhu, Morishita, Fitzgerald, Uyemura, and Matloubian.

We have only considered those arguments that Appellants actually
raised in the Briefs. Arguments Appellants could have made but chose not
to make in the Briefs have not been considered and are deemed to be
waived. See 37 C.F.R. § 41.37(c)(1)(vii)(2011).

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ISSUE 1
35 U.S.C. § 103(a): claims 1, 3, 4, 6, 16-21, 43, 45, 46, 48., 125, 129, 131,
135, and 137
Appellants assert their invention is not obvious over Morishita since
Morishita does not explicitly disclose a specific length of a channel region,
nor does Morishita indicate the proportions of the gate and the channel
region, illustrated in Figure 4, are drawn to proportion (App. Br. 8-10; Reply
Br. 2-3).
Appellants further argue the Examiner does not provide a sufficient
rationale as to why an ordinarily skilled artisan would have combined
Morishita’s MOSFET with Sandhu’s MRAM array and memory controller
but instead uses hindsight reasoning (App. Br. 10).
Issue 1a: Has the Examiner erred in finding the combination of
Sandhu, Morishita, and Cristoloveanu teaches or suggests “an active layer
having a thickness tSi and comprising a channel region, the channel region
having a length L, where L/tSi is between 11.8 and 25” as recited in
independent claim 1?
Issue 1b: Did the Examiner improperly combine the references of
Sandhu, Morishita, and Cristoloveanu?

ANALYSIS
We do not agree with Appellants. Although Appellants are correct to
state that the channel region is distinct from the gate (App. Br. 10) and
Morishita does not explicitly discuss the channel region length, an ordinarily
skilled artisan would have understood Morishita’s Figure 4 as depicting a
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thin film transistor wherein the length of the channel region 13, which is
positioned below and controlled by the gate 16, corresponds to the gate
length. Indeed, we agree with the Examiner’s findings and conclusions that
the teachings and suggestions of Morishita are sufficient to lead a skilled
artisan to find the channel region length is substantially equal to the gate
length. Indeed, even though the Figure 4’s scale, i.e., the ratio of thickness
and length of each layer, may not be reliable, we agree with the Examiner
that the edge relationship between the channel length and gate length
coincide and thus, a skilled artisan would find the gate length is substantially
equal to the channel length.
In light of this and Morishita’s further disclosure that the gate length
is 0.8 µm (and corresponds to the channel length) and a thickness of
crystalline silicon layer of 0.03µm or more and 0.7µm or less, we agree with
the Examiner that Morishita teaches or at least suggests L/tSi is between
11.8 and 25 (Ans. 4 and 16-17).
Additionally, Appellants have not provided sufficient argument or
evidence to persuade us the Examiner has used hindsight reasoning in
determining and did not provide a sufficient rationale for why a person of
ordinary skill in the art would have combined Morishita’s MOSFET with
Sandhu’s MRAM array and memory controller (App. Br. 10). Indeed, the
Examiner has articulated reasoning with a rational underpinning and
Appellants have not persuaded us the reasoning is in error.
Accordingly, Appellants have not persuaded us the Examiner erred in
finding the combination of Sandhu, Morishita, and Cristoloveanu teaches or
suggests the invention as recited in independent claim 1. Appellants relied
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on the arguments set forth for claim 1 in arguing the Examiner erred in
rejecting independent claims 43, 125, and 131 which recite a commensurate
limitation to the disputed limitation of claim 1. Therefore, for the reasons
set forth above, we are also not persuaded the Examiner erred in rejecting
claims 43, 125, and 131. Dependent claims 3, 4, 6, 16-21, 45, 46, 48, 129,
135, and 137 fall with their respective independent claims. Therefore, the
Examiner did not err in rejecting claims 1, 3, 4, 6, 16-21, 43, 45, 46, 48, ,
125, 129, 131, 135, and 137 under 35 U.S.C. § 103(a) for obviousness.

ISSUE 2
35 U.S.C. § 103(a): claims 7-10 and 49-52
Appellants assert their invention is not obvious over Sandhu,
Morishita, and Cristoloveanu because the combination of references does
not disclose “a geometry defined by two or more of tSi, TOX, and L; and the
geometry, the semiconductor of the active layer, and the oxide of the oxide
layer having been selected to limit a ratio ION/IOFF to more than 100 at
temperatures up to 125°C, where IOFF is a leakage current flowing through
the substrate and ION is a current flowing through the active layer” (App. Br.
11). Specifically, Appellants contend Cristoloveanu’s Figure 7 depicts drain
current not leakage current (App. Br. 12). Further, according to Appellants,
in its discussion of leakage current, Cristoloveanu does not disclose a
selection of the geometry of the device, the semiconductor of the device, or
the oxide of the oxide layer and that all these features be selected to limit a
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ratio ION/IOFF to more than 100 at temperatures up to 125°C (App. Br. 12;
Reply Br. 3-4).

Issue 2: Has the Examiner erred in concluding the combination of
Sandhu, Morishita, and Cristoloveanu teaches or suggests “a geometry
defined by two or more of tSi, TOX, and L; and the geometry, the
semiconductor of the active layer, and the oxide of the oxide layer having
been selected to limit a ratio ION/IOFF to more than 100 at temperatures up to
125°C, where IOFF is a leakage current flowing through the substrate and ION
is a current flowing through the active layer” as recited in claim 7?

ANALYSIS
We agree with the Examiner’s findings and conclusions and adopt
them as our own (Ans. 18-21). Specifically, we agree Cristoloveanu teaches
or at least suggests the drain current in the off-state would be a total leakage
current observed at the drain when the device is not active (or is “off”')
which would inherently include current components associated with any
substrate leakage current and any active layer leakage current (Ans. 19).
Thus, we agree with the Examiner that Cristoloveanu teaches or at least
suggests for any given IOFF, the substrate leakage current component would
be smaller than the total drain off-state leakage current shown in Figure 7
and accordingly, ratio ION/IOFF, with IOFF as the smaller substrate leakage
current would still be more than 100 at the recited temperatures (Ans. 19-
20).
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We further agree with the Examiner that Cristoloveanu teaches or at
least suggests a geometry, the semiconductor of the active layer, and the
oxide of the oxide layer are selected (Ans. 20-21). We additionally
emphasize we are not persuaded such a selection would be “uniquely
challenging or difficult for one of ordinary skill in the art” or “represented an
unobvious step over the prior art.” Leapfrog Enters., Inc. v. Fisher-Price,
Inc., 485 F.3d 1157, 1162 (Fed. Cir. 2007) (citing KSR, 550 U.S. at 418).
Moreover, we emphasize Appellants appear to be arguing the
references individually, when the Examiner is relying on the combination of
Sandhu, Morishita, and Cristoloveanu as teaching or at least suggesting the
invention as recited in claim 7 and commensurately recited in claim 9.
Appellants relied on the arguments set forth for claim 7 in arguing the
Examiner erred in rejecting claims 49 and 52 which recite a commensurate
limitation to the disputed limitation of claim 7. Therefore, for the reasons
set forth above, we are also not persuaded the Examiner erred in rejecting
claims 49 and 52.
Accordingly, we are not persuaded the Examiner erred in finding the
combination of Sandhu, Morishita, and Cristoloveanu teaches or suggests
the invention as recited in claim 7 and commensurately recited in claims 9,
49, and 52. Dependent claims 8, 10, 50, and 51were not separately argued
and thus fall with the claims from which they respectively depend.
Therefore, the Examiner did not err in rejecting claims 7-10 and 49-52 under
35 U.S.C. § 103(a) for obviousness over Sandhu, Morishita, and
Cristoloveanu.

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ISSUE 3
35 U.S.C. § 103(a): claims 11-15, 22-26, 53-65, and 138-144
Appellants assert their invention is not obvious over Sandhu,
Fitzgerald, Uyemura, and Matloubian because the combination does not
teach or suggest:
one or more P-channel transistors comprising a first portion of
the substrate, where the P-channel semiconductor device is
characterized by a gain ßp and a leakage current IOFF-P; one or more N
-channel transistors in communication with the one or more P-channel
transistors, the N -channel transistors comprising a second portion of
the substrate, where each N -channel transistor is characterized by a
gain ßn and a leakage current IOFF-N; and where, at a predetermined
temperature: ßp ≈ ßn; and IOFF-P ≈ IOFF-N

as recited in representative claim 11(App. Br. 12-13). Specifically,
Appellants contend none of the references teaches or suggests a beta
matched circuit where the beta matching is performed at a predetermined
temperature (App. Br. 13). According to Appellants, Fitzgerald discusses
symmetrical inverters, Uyemura discusses equations for transconductance
and symmetrical inverters, and Matloubian discusses an SOI transistor
model and an equation for a MOSFET channel circuit; however, none of
these references, alone or in combination, teach or suggest beta matching at
a predetermined temperature (id.).
Further, Appellants assert “the mere fact that a thing inherently
operates at a temperature does not mean that the temperature was determined
beforehand” (Reply Br. 4).

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Issue 3: Has the Examiner erred in concluding the combination of
Sandhu, Fitzgerald, Uyemura, and Matloubian teaches or suggests “where,
at a predetermined temperature: ßp ≈ ßn; and IOFF-P ≈ IOFF-N” as recited in
claim 11?

ANALYSIS
We agree with the Examiner’s findings and conclusions and adopt
them as our own. We highlight that we agree with the Examiner that the
combination of references “collectively teach the desirability of a
symmetrical design in a CMOS circuit device, the symmetrical design
including beta matching (i.e., ßp ≈ ßn . . .)” (Ans. 21). We further emphasize
we agree the circuit/device “would be inherently operating at a
predetermined temperature, one would consider the predetermined operating
temperature in designing the symmetrical, beta-matched CMOS
circuit/device” (id.).
Indeed, all of the relationships taught and suggested by the relied upon
references, Sandhu, Fitzgerald, Uyemura, and Matloubian, are true for the
operating temperature range of actual devices (see e.g., Matloubian pg.
1985, ¶Abstract). Therefore, we are not persuaded an ordinarily skilled
artisan would have found setting the characteristics at a predetermined
temperature (as broadly, but reasonable construed) unusually challenging or
beyond one of ordinary skill in the arts’ abilities.
Accordingly, we are not persuaded the Examiner erred in finding the
combination of Sandhu, Fitzgerald, Uyemura, and Matloubian teaches or
suggests the invention as recited in claim 11 and commensurately recited in
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independent claims 22, 53, and 61 and dependent claims 12-15, 23- 26, 54-
60, 62-65, and 138-144, not separately argued. Therefore, the Examiner did
not err in rejecting claims 11-15, 22- 26, 53-65, and 138-144 under
35 U.S.C. § 103(a) for obviousness over Sandhu, Fitzgerald, Uyemura, and
Matloubian.

DECISION
The Examiner’s rejections of claims 1, 3, 4, 6-26, 43, 45, 46, 48-65,
125, 129, 131, 135, and 137-144 under 35 U.S.C. § 103(a) is affirmed.

No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(1)(iv) (2011).

AFFIRMED

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