Ex Parte Chumbalkar et al

Patent Trial and Appeal Board

Sep 10, 2018

14055743 (P.T.A.B. Sep. 10, 2018)

UNITED STA TES p A TENT AND TRADEMARK OFFICE
APPLICATION NO. FILING DATE
14/055,743 10/16/2013
109808 7590 09/12/2018
LENOVO/P ANGRLE
Pangrle Patent, Brand & Design Law, P.C.
3500 W Olive Ave
3rd Floor
Burbank, CA 91505
FIRST NAMED INVENTOR
Nagananda Chumbalkar
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www .uspto.gov
ATTORNEY DOCKET NO. CONFIRMATION NO.
RPS920130066-US-NP 3135
EXAMINER
ARCOS, JEISON C
ART UNIT PAPER NUMBER
2113
NOTIFICATION DATE DELIVERY MODE
09/12/2018 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
brian@ppbdlaw.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte NAGANANDA CHUMBALKAR and
RODD. WALTERMANN
Appeal2018-001482
Application 14/055,743
Technology Center 2100
Before ST. JOHN COURTENAY III, JUSTIN BUSCH, and
JENNIFER L. McKEOWN, Administrative Patent Judges.
BUSCH, Administrative Patent Judge.
DECISION ON APPEAL
Pursuant to 35 U.S.C. § 134(a), Appellants appeal from the
Examiner's decision to reject claims 1-11 and 13-19, which constitute all
claims pending in this application. We have jurisdiction over the pending
claims under 35 U.S.C. § 6(b). We affirm.
CLAIMED SUBJECT MATTER
Appellants' invention is generally directed to baseboard management
controllers (BM Cs) and, more specifically to "technologies and techniques
Appeal2018-001482
Application 14/055,743
... for controller access to host memory." Spec. ,r 2. Claims 1 and 18 are
independent claims. Claim 1 is reproduced below:
1. A server comprising:
a circuit board;
a processor mounted to the circuit board;
a first operating system instructions executable by the
processor;
a storage subsystem accessible by the processor;
random access memory accessible by the processor;
a network interface operatively coupled to the processor;
a controller network interface;
a controller mounted to the circuit board and operatively
coupled to the controller network interface; and
second operating system instructions executable by the
controller;
wherein the controller comprises
circuitry that commences a debug process
responsive to receipt of information via the controller
network interface,
circuitry that alters a timer to halt a corresponding
reset operation that alters random access memory values
associated with the first operating system and stored in the
random access memory and,
circuitry that captures the random access memory
values stored in the random access memory, the random
access memory values being associated with a state of the
server, and
circuitry that transmits the values via the controller
network interface as part of the debug process.
REJECTIONS
Claims 1-6, 8, 11, 13, 15, and 18 stand rejected under 35 U.S.C. § 103
as obvious in view of Dube (US 2011/0093575 Al; Apr. 21, 2011), Official
Notice that systems include circuit boards to interconnect discrete elements,
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Application 14/055,743
Wadsworth (US 6,067,407; May 23, 2000), and Gomez (US 2009/0006915
Al; Jan. 1, 2009). Final Act. 2-7.
Claim 7 stands rejected under 35 U.S.C. § 103 as obvious in view of
Dube, Official Notice, Wadsworth, Gomez, and Wen (US 2013/0290789
Al; Oct. 31, 2013). Final Act. 7-8.
Claim 9 stands rejected under 35 U.S.C. § 103 as obvious in view of
Dube, Official Notice, Wadsworth, Gomez, and Lach (US 6,363,452 Bl;
Mar. 26, 2002). Final Act. 8.
Claim 10 stands rejected under 35 U.S.C. § 103 as obvious in view of
Dube, Official Notice, Wadsworth, Gomez, and Rentschler (US
2012/0146658 Al; June 14, 2012). Final Act. 8-9.
Claim 14 stands rejected under 35 U.S.C. § 103 as obvious in view of
Dube, Official Notice, Wadsworth, Gomez, and Azimi (US 2013/0099937
Al; Apr. 25, 2013). Final Act. 9.
Claim 16 stands rejected under 35 U.S.C. § 103 as obvious in view of
Dube, Official Notice, Wadsworth, Gomez, and Jones (US 2013/0139128
Al; May 30, 2013). Final Act. 9-10.
Claims 17 and 19 stand rejected under 35 U.S.C. § 103 as obvious in
view of Dube, Official Notice, Wadsworth, Gomez, and De Oliveira (US
2006/0259612 Al; Nov. 16, 2006). Final Act. 10-11.
ANALYSIS
We have reviewed the Examiner's rejections in light of Appellants'
arguments that the Examiner erred. In reaching this decision, we have
considered all evidence presented and all arguments Appellants made.
Arguments Appellants could have made, but chose not to make in the Briefs,
are deemed waived. See 37 C.F.R. § 4I.37(c)(l)(iv).
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Application 14/055,743
CLAIMS 1-11 AND 13-17
Appellants argue claims 1-11 and 13-17 as a group. See App. Br. 5-
11. We select claim 1 as representative of the group. See 37 C.F.R.
§ 4I.37(c)(l)(iv).
The Examiner finds Dube teaches each of the components of the
server recited in claim 1 except for the circuit board, for which the Examiner
takes Official Notice "that in order to interlink all the discrete elements in
the system it is necessary for the system to include a circuit board." Final
Act. 2-3 (citing Dube ,r,r 8-9, 11, 19-21, Figs. 2-3).
Of particular note, the Examiner finds Dube discloses "a network
interface controller as part of a[] baseboard management controller" (BMC).
Final Act. 3 (citing Dube ,r 8, Fig. 3 (162)); see Ans. 5-6 (explaining that
Dube, not Wadsworth, is relied on as teaching the controller recited in claim
1 ). The Examiner further finds Dube discloses "a system which includes a
BMC which allows the process of debugging a system by emulation either
external or internal interfaces and the system includes network interface for
communication purposes, wherein the BMC includes its own operating
system." Ans. 4--5.
The Examiner finds Dube fails to disclose the particular debugging
functions recited in the claim, but relies on a combination of Wads worth and
Gomez to teach those functions. Final Act. 3--4 ( citing Gomez ,r,r 5, 28,
Abstract; Wadsworth 2:15-24, 10:14--16, Fig. 10). The Examiner finds the
combination of the Official Notice taken with Dube's system teaches the
recited elements and, one "can incorporate the functionality of Wadsworth
[which] provides a system with the functionality to perform data dumps."
Ans. 5.
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Application 14/055,743
Appellants argue the Examiner erred in relying on Official Notice to
teach the recited circuit board. App. Br. 6. Appellants further assert
combining Wadsworth with Gallagher makes no sense. App. Br. 8.
Although it does not appear Appellants substantively challenge the taking of
Official Notice, the Examiner supported the Official Notice by citing U.S.
Patent Application No. 2001/0011314 to Gallagher. See Advisory Act. 2
( mailed March 15, 2017); Ans. 3 ( explaining Gallagher is not cited as prior
art, but merely "as evidence that that the system discloses a motherboard as
a structure for connecting all elements in the computer system ... providing
evidence that [it] is common knowledge ... that multiple discreet elements
are mounted to a circuit board" ( citations omitted)). Regarding the
Examiner's reliance on Official Notice, we find no statement in Appellants'
Briefs that the claimed "circuit board" was not well known in the art at the
time of Appellants' invention. 1 Claim 1. Arguments not made are waived.
See 37 C.F.R. § 4I.37(c) (l)(iv).
The Examiner does not propose combining Gallagher's teachings with
any of the other cited prior art. Moreover, Gallagher supports the
Examiner's taking of Official Notice that circuit boards are commonly used
1 To traverse the Examiner's taking of Official Notice, Appellants must
specifically point out the supposed errors in the Examiner's action, which
would include stating why the noticed fact is not considered to be common
knowledge or well-known in the art. See MPEP § 2144.03 ( emphasis
added). An adequate traverse of the Examiner's taking of Official Notice
must contain adequate information or argument to create on its face a
reasonable doubt regarding the circumstances justifying the Examiner's
notice of what is well known to one of ordinary skill in the art. In re Boon,
439 F.2d 724, 728 (CCPA 1971).
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to connect computing elements such as those recited in claim 1. Therefore,
we are not persuaded the Examiner erred in taking Official Notice.
Appellants also contend Wadsworth does not teach a controller
mounted to a circuit board because Wadsworth is directed to an interface
board designed to connect a peripheral to a network and operate
independently of a PC such that placing Wadsworth's interface board on a
circuit board of a server "makes no sense." App. Br. 6-7 (emphasis
omitted); Reply Br. 3--4. Appellants further assert Wadsworth fails to teach
a controller mounted on a circuit board, as recited in claim 1, because the
record provides no reason to combine Wadsworth's interface board with a
circuit board. App. Br. 9-10; Reply Br. 4.
Appellants' argument that Wadsworth does not teach a controller
mounted to a circuit board is not persuasive because the Examiner finds
Dube in combination with the Official Notice taken teaches the recited
controller mounted to the circuit board. See Final Act. 3 ( citing Dube ,r 8,
Fig. 3 (162)); see Ans. 5---6 (explaining that Dube, not Wadsworth, teaches
the controller recited in claim 1). For the same reason, Appellants'
contention that the record lacks a reason one would have used Wadsworth's
interface board as the recited controller in the proposed combination is
misplaced. The Examiner finds Wadsworth teaches the particular debugging
steps recited in claim 1 and proposes "incorporat[ing] the functionality of
Wadsworth['s] network interface board" so that "the combination of Dube
with Wadsworth provides a system with the functionality to perform data
dumps." Ans. 5 (emphasis added).
Finally, Appellants argue Wadsworth's interface board is connected to
a peripheral device (not a workstation) and Wadsworth's SRAM temporarily
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stores data packets rather than the recited random access memory values
associated with the first operating system, so Wadsworth does not teach
dumping workstation memory. App. Br. 9; Reply Br. 2-3.
Wadsworth's interface board is designed to be attached to peripheral
devices and, therefore, provide interface functions on a single interface
board over a network and without the need for a dedicated computer to
interface between the network and the device. Wadsworth 1: 16-26.
Wadsworth is directed to providing "dump and/or debug facilitates for a
network interface board which can be carried out remotely," thus
overcoming the problem of needing to be "physically co-located with the"
nonfunctioning interface board. Wadsworth 1:63-2:7. Wadsworth's
interface boards can then receive dump/debug network packets from a
workstation over a network, initiate the desired dump and/ or debug functions
using the included "interrupt-driven network driver program," and transmit
the results back over the network to the requesting workstation. Wadsworth
2: 12-24. Wadsworth is able to execute the dump and/or debug functions
regardless of the state of the interface board because the interface board
access the peripheral device at the physical network layer as long as the
device drive is functioning. Wadsworth 2:42-65. Furthermore,
Wadsworth's debug and dump facilities may store data to or retrieve data
from any memory in the interface board. Wadsworth 11 :2-5 ("Note that any
location accessible by microprocessor 11 can be stored to or retrieved from,
e.g., microprocessor registers, DRAM 15, interface controllers 22 and 25,
and so on.").
Accordingly, we agree with Appellants that Wadsworth, alone, does
not disclose dumping workstation memory because Wadsworth discloses
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connecting its interface board between a peripheral device and a network
instead of needing a dedicated computer to manage the peripheral device.
See Wadsworth 1: 16-26, 5 :46-50. However, the Examiner relies on
Wadsworth's disclosure of particular debugging and dumping features only
for teaching the debugging functionality recited in claim 1. Final Act. 3--4;
Ans. 5. The Examiner relies on the combined teachings and suggestions of
Dube, Official Notice, Gomez, and Wadsworth to teach the subject matter of
claim 1.
Specifically, as explained above, the Examiner proposes
"incorporat[ing] the functionality ofWadsworth['s] network interface board
[ so that] the combination of Dube with Wadsworth provides a system with
the functionality to perform data dumps." Ans. 5. Wadsworth explicitly
states that "[i]n implementing the present invention, the precise hardware
construction of the interface board is of less importance than the software
construction." Wadsworth 5:63---65. The Examiner's proposed combination
of incorporating Wadsworth's memory dump function into Dube's system,
therefore, results in dumping any of the memory accessible to Dube' s
controller. Accordingly, applying Wadsworth's teaching of debugging or
dumping data from the device to which the controller is attached to Dube' s
system would suggest dumping any of the memory in Dube' s system,
including "the random access memory values [ associated with the first
operating system and] stored in the random access memory." See Final
Act. 4; Ans. 5---6.
As mentioned above, Appellants argue claims 1-11 and 13-1 7 as a
group. Accordingly, for the above reasons, we are not persuaded the
Examiner erred in rejecting claims 1-11 and 13-17 under 35 U.S.C. § 103.
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CLAIMS 18 AND 19
Appellants present substantively similar arguments that the proposed
combination fails to teach or suggest storing "values in the random access
memory that are associated with the first operating system," which is recited
in both independent claims 1 and 18. Appellants present no other separate
substantive arguments with respect to claims 18 and 19. Therefore, for the
same reasons discussed above with respect to claim 1, we are not persuaded
the Examiner erred in rejecting claims 18 and 19 as obvious under 35 U.S.C.
§ 103.
DECISION
We affirm the Examiner's decision to reject claims 1-11 and 13-19
under 35 U.S.C. § 103 as obvious.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(l )(iv).
AFFIRMED
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