Ex Parte CHEN et al

Patent Trial and Appeal Board

May 18, 2018

14526654 (P.T.A.B. May. 18, 2018)

UNITED STA TES p A TENT AND TRADEMARK OFFICE
APPLICATION NO. FILING DATE
14/526,654 10/29/2014
23125 7590 05/22/2018
NXP USA, Inc.
LAW DEPARTMENT
6501 William Cannon Drive West TX30/0E62
AUSTIN, TX 78735
FIRST NAMED INVENTOR
WEIZECHEN
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www .uspto.gov
ATTORNEY DOCKET NO. CONFIRMATION NO.
AM21031TP 5993
EXAMINER
RAHMAN, KHATIB A
ART UNIT PAPER NUMBER
2813
NOTIFICATION DATE DELIVERY MODE
05/22/2018 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address( es):
ip.department.us@nxp.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte WEIZE CHEN, SUNG-TAEG KANG, and
PATRICE M. PARRIS
Appeal2017-007357
Application 14/526,654
Technology Center 2800
Before LINDA M. GAUDETTE, DONNA M. PRAISS, and
MONTE T. SQUIRE, Administrative Patent Judges.
PRAISS, Administrative Patent Judge.
DECISION ON APPEAL 1
STATEMENT OF THE CASE
This is an appeal under 35 U.S.C. § 134(a) from the final rejection of
claims 1---6 and 13-16. We have jurisdiction under 35 U.S.C. § 6.
We AFFIRM.
1 This decision makes reference to the Specification filed October 29, 2014
("Spec."), the Final Office Action dated March 16, 2016 ("Final Act."), the
corrected Appeal Brief filed August 31, 2016 ("Appeal Br."), the
Examiner's Answer dated February 9, 2017 ("Ans."), and the Reply Brief
filed April 10, 2017 ("Reply Br.").
Appeal2017-007357
Application 14/526,654
The subject matter of this appeal relates to semiconductor memories
and, more particularly, non-volatile memories (NVMs) that have a split gate.
Spec. i-f 1. Claim 1 is illustrative (disputed elements italicized):
1. A method, using a semiconductor substrate, of making
a semiconductor structure having a memory region and a logic
reg10n, compnsmg:
forming a first dielectric layer over the memory region;
forming a second dielectric layer over a first portion of the
logic region;
forming a first polysilicon layer over the first dielectric
layer and the second dielectric layer;
depositing a hard mask layer over the first polysilicon
layer;
forming an opening in the first polysilicon layer and the
hard mask layer in the memory region;
forming a charge storage layer over the hard mask layer
and in the opening;
forming a second polysilicon layer over the charge storage
layer including in the opening;
etching the second polysilicon layer to remove the second
polysilicon layer from over the hard mask layer while leaving a
portion of the second polysilicon layer in the opening, wherein
the portion of the second polysilicon layer has a single height;
removing the hard mask layer over the first polysilicon
layer while the portion of the second polysilicon layer remains at
the single height; and
etching the first polysilicon layer to form a first gate over
the first portion of the logic region and etching the second
polysilicon layer in the opening to define an edge of a control
gate of a first split gate non-volatile memory (NVM) cell and an
edge of a control gate of a second split gate NVM cell while the
portion of the second polysilicon layer remains at the single
height.
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Application 14/526,654
Appeal Br. 17 (Claims Appendix).
The Examiner maintains, and Appellant2 appeals, the following
rejections under 35 U.S.C. § 103:
1. Claims 1, 2, 10, 11, and 13-16 over Herrick (US 2010/0099246
Al, published Apr. 22, 2010) in view of Steimle (US 2008/0121974 Al,
published May 29, 2008) and Shroff (US 2013/0137227 Al, published May
30, 2013);
2. Claims 3-5 and 7-9 over Herrick in view of Steimle and Shroff
and further in view of Fang (US 2014/0167140 Al, published June 19,
2014);
3. Claim 6 over Herrick in view of Steimle, Shroff, and Fang further
in view of Hall (US 2013/0267074 Al, published Oct. 10, 2013) and Nansei
(US 2009/0020799 Al, published Jan. 22, 2009);
4. Claims 17 and 18 over Herrick in view of Shroff; and
5. Claims 19 and 20 over Herrick in view of Steimle.
Ans. 2; Appeal Br. 12.
OPINION
After review of the arguments and evidence presented by both
Appellant and the Examiner, we affirm the stated rejections for the reasons
provided in the Final Action and Answer. We add the following primarily
for emphasis.
2 The Appellant is the Applicant, Freescale Semiconductor, Inc., which is
also identified as the real party in interest. Appeal Br. 3.
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Appeal2017-007357
Application 14/526,654
Rejection 1
It is the Examiner's position that claims 1, 2, 10, 11, and 13-16 are
unpatentable as obvious over Herrick in view of Steimle and Shroff for the
reasons stated on pages 4--10 of the Final Action.
In the Appeal Brief, Appellant argues the subject matter of claims 1,
2, 10, 11, and 13-16 as a group. In accordance with 37 C.F.R.
§ 41.37(c)(l)(iv), claims 2, 10, 11, and 13-16 will stand or fall together with
claim 1, which is representative of the group.
Appellant contends that the rejection is in error because none of the
cited references discloses a second polysilicon layer that remains at a single
height as required by claim 1. Appeal Br. 13. According to Appellant, it
would not have been obvious to combine Herrick and Steimle to keep the
second polysilicon layer at a single height because neither reference teaches
fabricating devices where the second polysilicon layer is not etched back
while a nitride layer is in place. Id. at 14. Appellant also contends that if
Herrick's second polysilicon layer is not etched back before the nitride layer
is removed, subsequent etching of the second polysilicon layer would
adversely affect source/drain regions of the logic device in the absence of
the nitride layer requiring additional process steps, increasing cost, and
degrading performance. Id.
The Examiner responds that a skilled artisan would have been
motivated to modify Herrick's NVM region such that the control gate is
higher than the select gate in view of Shroff' s disclosure of improved
performance with a control gate that remains higher than the select gate in
the NVM region that is integrated on the same substrate with the logic
region. Ans. 2-3. The Examiner further responds that such a modification
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Appeal2017-007357
Application 14/526,654
of Herrick also would have been recognized by one having ordinary skill in
the art as having an associated benefit of saving cost and simplifying the
manufacturing process because the process step of etching of the second
polysilicon layer to reduce the height of the control gate relative to the select
gate is omitted. Id. at 3. The Examiner clarifies that the stated rejection
does not rely upon Steimle for the modification of Herrick's method, but,
rather, for teaching that etch back planarization technique is an alternative to
chemical mechanical polish technique (CMP). Id. at 4. According to the
Examiner, the combination of Herrick, Steimle, and Shroff to achieve a
control gate higher than the select gate in the NVM region by not
implementing Herrick's step shown in Figure 6 results in the height of the
second polysilicon layer staying the same height of the second polysilicon
layer. Id. at 3. The Examiner responds to Appellant's contention that
Shroff' s control gate has two different heights by finding that the uppermost
surface of the second polysilicon layer in Shroff remains at the same level
throughout the process based on the height from the base level of the control
gate to the uppermost point of the control gate in a vertical direction. Id. at 4
(citing Shroff Figs. 3-10).
In the Reply Brief, Appellant contends that Shroffs control gate has
multiple levels formed by a conformal deposition a metal layer over the
select gate. Reply Br. 2 (citing Shroff Figs. 8 and 9). Appellant also
contends that Steimle' s etch back planarization technique would not be
compatible to remove Shroff s second metal layer because the highest
portions of Shroff s metal layer would be removed first, thereby destroying
Shroff's multi-tiered control gate structure and performance advantages
along with it. Id. at 2-3. Appellant additionally argues that Shroffs control
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Appeal2017-007357
Application 14/526,654
gate does not have a single height due to the multiple levels of the structure,
thus it has more than a single second height. Id. at 3.
We are not persuaded of reversible error in the Examiner's rejection
of claims 1, 2, 10, 11, and 13-16 based on the cited record on appeal.
Appellant does not dispute the Examiner's finding (Ans. 2-3) that
Shroff teaches improved performance with a control gate that remains higher
than the select gate in the NVM region that is integrated on the same
substrate with the logic region. Instead, Appellant contends (Reply Br. 3)
that Shroff s control gate has more than one height based on its shape. The
difficulty with Appellant's argument is that the rejection is based on
Herrick's method being modified by the teaching of Shroff that a control
gate that remains higher than the select gate in the NVM region improves
performance. Herrick's method as modified by the teaching of Shroff to
maintain a control gate that is higher than the select gate would maintain
Herrick's second polysilicon layer (26) which is shown in Herrick's Figure 5
as having a uniform level shape. Appellant's argument that using Steimle's
etch back planarization technique in Shroff' s method would eliminate
Shroff s multi-tiered control gate structure (Reply Br. 2-3) is not persuasive
because it does not address the stated rejection, namely modification of
Herrick's control gate structure rather than Shroff' s control gate structure.
Accordingly, we affirm the stated rejections of claims 1, 2, 10, 11, and 13-
16 under 35 U.S.C. § 103.
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Application 14/526,654
Rejection 2
It is the Examiner's position that claims 3-5 and 7-9 are unpatentable
as obvious over Herrick in view of Steimle and Shroff and further in view of
Fang for the reasons stated on pages 10-16 of the Final Action.
In the Appeal Brief, Appellant contends that the rejection is in error
for the same reasons as claim 1 from which claims 3-5 and 7-9 depend and
because "Fang does not include the features of claims 3-5 and 7-9 that are
not found in Herrick, Steimle, or Shroff, alone or in combination." Appeal
Br. 15.
Appellant's sweeping statement that the features of the dependent
claims are not found in the cited references is insufficient to state a separate
argument for claims 3-5 and 7-9. See 37 C.F.R. § 41.37(c)(iv) (requiring,
for each argument, "the basis therefor, with citations of the statutes,
regulations, authorities, and parts of the Record relied on" and further
requiring that the "arguments shall explain why the examiner erred as to
each ground of rejection"); see also In re Lovin, 652 F.3d 1349, 1357 (Fed.
Cir. 2011).
Because we are not persuaded of error in the Examiner's rejection of
claim 1 over the combination of Herrick, Steimle, and Shroff for the reasons
discussed above, we likewise affirm the Examiner's decision to reject claims
3-5 and 7-9 under 35 U.S.C. § 103.
Rejection 3
It is the Examiner's position that claim 6 is unpatentable as obvious
over Herrick in view of Steimle, Shroff, and Fang further in view of Hall
and N ansei for the reasons stated on pages 16-18 of the Final Action.
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Appeal2017-007357
Application 14/526,654
In the Appeal Brief, Appellant argues that the Examiner erred for the
same reasons claim 1 is distinguishable over the cited art and because "Fang,
Hall and N ansei do not include the features of claim 6 that are not found in
Herrick, Steimle, or Shroff, alone or in combination." Appeal Br. 16.
Appellant's assertion is insufficient to state a separate argument for
claim 6. In re Lovin, 652 F.3d at 1357. Because we are not persuaded of
error in the Examiner's rejection of claim 1 over the combination of Herrick,
Steimle, and Shroff for the reasons discussed above, we likewise affirm the
Examiner's decision to reject claim 6 under 35 U.S.C. § 103.
Rejection 4
It is the Examiner's position that Herrick and Shroff suggest the
subject matter of claims 17 and 18 for the reasons stated on pages 18-21 of
the Final Action.
In the Appeal Brief, Appellant argues that the Examiner erred for the
same reasons claim 1 is distinguishable, namely that Herrick's control gate
has a second height less than the first height of the select gate and Shroff s
control gate has multiple heights, not a single height. Appeal Br. 16.
Because we are not persuaded of error in the Examiner's rejection of
claim 1 over Herrick as modified by the teachings of Shroff, we likewise
affirm the Examiner's decision to reject claims 17 and 18 under 35 U.S.C.
§ 103 for the same reasons discussed above in connection with claim 1.
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Appeal2017-007357
Application 14/526,654
Rejection 5
It is the Examiner's position that Herrick and Steimle suggest the
subject matter of claims 19 and 20 for the reasons stated on pages 21-23 of
the Final Action.
In the Appeal Brief, Appellant argues that the rejection is in error
because "the control gate in Herrick has a second height less than the first
height of the select gate." Appeal Br. 16. Appellant also contends that the
features of claim 20 further distinguish it from the cited references. Id.
We are not persuaded of reversible error on the part of the Examiner
because the Examiner's finding (Final Act. 22) that Herrick's second
polysilicon layer 26 (control gate) unetched is higher than Herrick's first
polysilicon layer 18 (select gate) in Figure 5 as required by claim 19 is
supported by the record. Herrick Fig. 5. In the Answer, the Examiner
further includes the teachings of Schroff as the reason for modifying
Herrick's method in Herrick and Steimle's combination by skipping the step
shown in Herrick's Figure 6 as in the rejection of claim 1. Ans. 5. The
Examiner finds that Herrick's method so modified results in the second
polysilicon layer remaining at the same height level (height of 26 in Figure
5), which is higher than the height of the first polysilicon layer (height of 18
in Figure 5), and remaining the same in subsequent steps in the modified
method such that select gate 3 8 is formed of the first polysilicon layer, the
control gate 34 is formed of the second polysilicon layer, and the control
gate 34 is higher than the height of select gate 38. Id. at 5---6.
Appellant does not address the Examiner's rejection of claim 19 in the
Reply Brief.
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Appeal2017-007357
Application 14/526,654
Because we are not persuaded of error in the Examiner's rejection of
claim 1 over Herrick and Steimle as modified by the teachings of Shroff, we
likewise affirm the Examiner's decision to reject claim 19 under 35 U.S.C.
§ 103 for the same reasons discussed above in connection with claim 1.
Regarding claim 20, Appellant's assertion is insufficient to state a
separate argument from that presented for claim 6. In re Lovin, 652 F .3d at
1357.
For the reasons discussed above, we likewise affirm the Examiner's
decision to reject claims 19 and 20 under 35 U.S.C. § 103.
DECISION
For the foregoing reasons, we affirm all of the Examiner's rejections
under 35 U.S.C. § 103.
TIME PERIOD FOR RESPONSE
No time period for taking any subsequent action in connection with
this appeal maybe extended under 37 C.F.R. § 1.136(a)(l).
ORDER
AFFIRMED
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